Himax Technologies, Inc.

United Microelectronics Corp.

National Yang Ming Chiao Tung University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Amazing Microelectronic Corporation

Amazing Microelectronics Corp.

Amazing Microelectric Corp.

Tung-Yang Chen

Ming-Dou Ker

Cheng-Cheng Yen

Ryan Hsin-Chin Jiang

Tien-Hao Tang

Hun-Hsien Chang

Hsing-Chou Hsu

Chi-Sheng Liao

Cheng-Ming Lee

Sheng-Fan Yang

James Jeng-Jie Peng

Woei-Lin Wu

Ching-Ling Tsai

Kun-Hsien Lin

Chung-Yu Wu

Shiao-Shien Chen

Zi-Ping Chen

Shih-Fan Chen

Jui-Ni Lee

A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal. Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

Silicon-controlled rectification device with high efficiency

A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block, and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.

Method for fabricating a planar micro-tube discharger structure

A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.

Self-reset transient-to-digital convertor and electronic product utilizing the same

The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.

Planar mirco-tube discharger structure and method for fabricating the same

A noise filter circuit for an IC is provided. The noise filter circuit comprises a decoupling unit coupled to a power pad of the IC and a current amplifier circuit coupled to the decoupling unit and the power pad of the IC. The decoupling unit generates a first current in response to a transient voltage being on the power pad of the IC. The current amplifier circuit drains a second current from the power pad of the IC according to the first current.

On-chip noise filter circuit

The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Impedance design method

An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.

Electrostatic discharge protection device structure

The present invention provides a signal analyzing method for an electronic device having an on-chip network and an off-chip network. Compared with the conventional signal analyzing method for an electronic device having an on-chip network and an off-chip network, the signal analyzing method of the present invention is able to provide a complete electrical connection and accurate electrical characteristics for an electronic device having an on-chip network and an off-chip network.

Signal analyzing method for electronic device having on-chip network and off-chip network

A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.

Method for predicting and debugging EMI characteristics in IC system and related machine-readable medium

The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

A circuit board includes a signal line plane and a reference plane. The signal line plane has at least a first transmission line and a second transmission line formed thereon. The reference plane has a conductive region and at least a non-conductive region. The first transmission line and the second transmission line overlap the conductive region in a thickness direction of the circuit board. The non-conductive region includes at least a first part and a second part connected to the first part, where the second part is positioned between the projection of the first transmission line on the reference plane and the projection of the second transmission line on the reference plane, and has no intersection with at least one of the projection of the first transmission line and the projection of the second transmission line.

Circuit board with a reference plane having multi-part non-conductive regions for decreased crosstalk

An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability. Accordingly, by properly adjusting the breakdown voltage of ESD device within I/O circuit, i.e. adjusting the distance between the edge of n-well and the battlement layout pattern of heavily doped regions, it will help to reduce the chip area and improve the ESD reliability.

ESD device layout for effectively reducing internal circuit area and avoiding ESD and breakdown damage and effectively protecting high voltage IC

A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.

Transient detection circuit

An ESD protection circuit including a discharge device, a first detection circuit, and a second detection circuit. The discharge device provides a discharge path between a first power rail and a second power rail when the discharge device is activated. The discharge device stops providing the discharge path when the discharge device is de-activated. The first detection circuit is coupled between the first and the second power rails. The first detection circuit activates the discharge device when an ESD event occurs in the first power rail. The second detection circuit de-activates the discharge device when the ESD event does not occur in the first power rail.

Growing community of inventors

Tainan County, Taiwan

Tung-Yang Chen