Spansion Llc.

Cypress Semiconductor Corporation

Tung-Sheng Chen

Shenqing Fang

Chun Chen

Di Li

Tim Thurgate

A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

Apparatus and method for rounded ONO formation in a flash memory device

Embodiments of the present technology are directed toward gate sidewall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewalls of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate corners.

Edge rounded field effect transistors and methods of manufacturing

A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.

Self-aligned NAND flash select-gate wordlines for spacer double patterning

A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

Method to improve charge trap flash memory core cell performance and reliability

A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.

Memory with extended charge trapping layer

Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.

Growing community of inventors

Cupertino, CA, United States of America

Tung-Sheng Chen