United Microelectronics Corp.

Powerchip Semiconductor Corporation

National Science Council

Tung-Po Chen

Yung-Chang Lin

Hong-Tsz Pan

Jacob Chen

Jih-Wen Chou

Keh-Ching Huang

Tony Lin

Wen-Yi Hsieh

Chen-Chiu Hsue

Chun-Yen Chang

Tong-Yu Chen

Ko-Hsing Chang

Jason Jyh-shyang Jenq

Bing-Chang Wu

Tan-Fu Lei

Tz-Guei Jung

Tung-Ming Lai

Kai-An Hsueh

Ming-Yin Hao

Tzu-Min Peng

Wen-Ji Chen

Sheng-Hone Zheng

A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.

Method for manufacturing gate dielectric layer

A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.

Method for manufacturing one-time electrically programmable read only memory

A process for forming high temperature stable self-aligned suicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal suicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal suicide layer profile can be ensured even if subsequent high temperature processing operations are performed.

Process for forming high temperature stable self-aligned metal silicide layer

A method for manufacturing an embedded DRAM with self-aligned borderless contacts is provided. The method comprises providing a substrate having a first device region and a second device region. The first device region comprises a first transistor and the second device region has a second transistor. A silicide block layer is formed over the second device region. An etching stop layer covers all device regions. A mask layer covers the first device region. Then the etching stop layer not covered by the mask layer is removed. A first dielectric material layer is formed on all the device regions and therein a first contact window is on the second device region. A second dielectric material layer is next formed and therein a second contact window is on the second device region. A third dielectric material layer is formed and therein at least a third contact window is coupled to the first transistor of the first device region. A borderless contact is consisted of the contact window coupled to the substrate and a metallic node on the contact window.

Method for fabricating an embedded DRAM with self-aligned borderless contacts

A method for manufacturing a semiconductor device is disclosed. The method can reduce thermal budget in node contact application. It includes mainly the following processes. A substrate is first provided, then a dielectric layer is formed over the substrate. Next, a node contact opening through the dielectric layer to top surface of the substrate is formed by coating the dielectric layer with a photoresist layer, patterning the photoresist layer with pattern of a node contact by exposure and development, then etching the dielectric layer until top surface of said substrate exposed using said patterned photoresist layer as a mask. Subsequently, the photoresist layer is removed. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).

Method for reducing thermal budget in node contact application

A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a lightly doped drain is subsequently formed in the substrate. Next, a second spacer is formed on the first spacer. Finally, a heavily doped drain is formed in the substrate. The present invention can enhance stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Method for forming MOSFET

A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.

Method of forming borderless contact

The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor. The portion of the first ion implantation layer that is not covered by the second ion implantation layer is used as a lightly doped drain (LDD). The protection layer is used to protect the surface of the silicon substrate from being etched during the RCA cleaning process so as to prevent an increase of the electrical resistance of the LDD.

Method of forming a MOS transistor

A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

Salicide formation process

A method of fabricating a CMOS transistor using Si&mdash;B layer to form a source/drain extension junction is disclosed. The fabrication includes the steps as follows; First, a p-type semiconductor substrate and an n-well region are provided. Afterwards, a shallow trench isolation (STI) is formed into the p-type semiconductor substrate and the n-well region, thereby forming a plurality of active regions therebetween. A channel is formed into the p-type semiconductor substrate and the n-well region. Then, a PMOSFET gate pattern and an NMOSFET gate pattern are formed over the p-type semiconductor substrate and the n-well region. A first defined photoresist layer is formed over the n-well region. Afterwards, the n,-type dopant is implanted into the p-type semiconductor substrate to form an n,-type lightly doped source/drain. Then the first defined photoresist layer is removed. A first dielectric layer is deposited over the p-type semiconductor substrate and the n-well region. A second defined photoresist layer is formed over the first dielectric layer. Afterwards, a portion of the first dielectric layer is firstly etched over the n-well region. Then an offset spacer is formed on the n-well region during a portion of the first dielectric layer etching step. Next, the second defined photoresist layer is removed. A Si&mdash;B (silicon-boron) layer is deposited over the n-well region and the first dielectric layer. The Si&mdash;B layer is oxidized to form a BSG layer, thereby firstly diffusing boron atoms into the n-well region to form a p,-type lightly doped source/drain. Afterwards, a second dielectric layer is deposited on the BSG layer. Next, a first BSG spacer and a second BSG spacer are formed, thereby etching a portion of the second dielectric layer, a portion of the BSG layer, and secondly etching a portion of the first dielectric layer. Afterwards, an n,-type heavily doped source/drain is formed into the p-type semiconductor substrate. Next, a p,-type heavily doped source/drain is formed into the n-well region. Finally, the first BSG spacer is annealed, thereby secondly diffusing boron atoms into the bottom region of the first BSG spacer to form a source/drain extension junction in a PMOSFET.

Method of fabricating CMOS using Si-B layer to form source/drain extension junction

A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

Method of fabricating field effect transistor

In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

Method of forming salicide in embedded dynamic random access memory

A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.

Method for forming polycide dual gate

A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.

Manufacturing method capable of preventing corrosion and contamination of MOS gate

A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate, followed by forming a gate oxide layer and a conductive layer over the substrate. An anti-reflective coating is then formed on the conductive layer. After patterning to etch the anti-reflective coating and the conductive layer, a gate region is thus formed. A dielectric layer is formed over the gate region, and is then subjected to etching back, therefore forming an offset spacer on sidewall of the gate region while simultaneously removing surface oxide of the anti-reflective coating. Finally, anti-reflective coating is removed.

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Taichung, Taiwan

Tung-Po Chen