Hewlett-packard Development Company, L.p.

Panta Systems, Inc.

Hewlett-packard Company

Advanced Green Computing Machines-ip, Limited

Other

Syrus Ziai

Emendable Assets Limited Liability Company

Tung M Nguyen

Fong Pong

Lance Warren Russell

Richard Au

Pradip Kulkarni

Kenneth Mark Wilson

Mukul Kumar

Lu Xu

Adhir Potdar

David H Nguyen

James M Mott

Paul Joseph Jordan

Eric Pouyoul

Mallikarjunan Mahalingam

Eric Christopher Anderson

Tipatat Chennavasin

David M Bradley

Greg Grohoski

Ram Gupta

Jean-Christophe Roger Hugly

Matthew Humphreys

Adam Drobot

Al Chang

Syed Najaf Rizvi

Najaf Rizvi

Andrew Spray

A multi-node computer system, comprising: a plurality of nodes, a system control unit and a carrier board. Each node of the plurality of nodes comprises a processor and a memory. The system control unit is responsible for: power management, cooling, workload provisioning, native storage servicing, and I/O. The carrier board comprises a system fabric and a plurality of electrical connections. The electrical connections provide the plurality of nodes with power, management controls, system connectivity between the system control unit and the plurality of nodes, and an external network connection to a user infrastructure. The system control unit and the carrier board provide integrated, shared resources for the plurality of nodes. The multi-node computer system is provided in a single enclosure.

High density multi node computer with improved efficiency, thermal control, and compute performance

High density multi node computer with integrated shared resources

Described herein is technology for, among other things root image caching and indexing for block-level distributed application management. The technology involves storing blocks of a root image on a first storage unit and storing blocks of leaf images on respective second storage units. The leaf images include additional data blocks not previously contained in the root image and changes made by respective compute nodes to the blocks of the root image. The technology includes caching blocks of the root image that have been accessed by at least one compute node. The technology also includes receiving indexing results pertaining to the root image from one compute node and providing the results for other compute nodes.

Root image caching and indexing for block-level distributed application management

Described herein is technology for, among other things virus scanning for block-level distributed application management. The technology involves storing blocks of a root image on a first storage unit and storing blocks of leaf images on respective second storage units. The leaf images include additional data blocks not previously contained in the root image and changes made by respective compute nodes to the blocks of the root image. The technology includes receiving a notification from one of the compute nodes that the root image has been scanned for viruses and providing the notification to other compute nodes.

Virus scanning for block-level distributed application management

Client node caching in a global file service. A client node receives a leaf image from a remote storage node storing a base image that is read-only accessible to the client node. The leaf image has a portion of the base image modified by the client node. The client node stores the leaf image in a cache on the client node. Unmodified portions of the base image are accessed from the remote storage node. Modified portions of the base image are accessed from the cache. The leaf images may comprise a branch modification log having portions of the base image modified by the client node and a metadata structure. The metadata structure has pointers to the modified data in the branch modification log and pointers to data unmodified by the client node in the base image. Alternatively, the leaf images may comprise a change volume for changes made to the base image by the client node.

Client side caching in a global file system

An embodiment of the present invention is directed to an apparatus for sharing memory among a plurality of compute nodes. The apparatus includes a memory, a plurality of interfaces for coupling the apparatus with the compute nodes, a switching fabric coupled with the interfaces, and a processor coupled with the switching fabric and the memory. The processor is operable to assign a portion of the memory to a particular compute node for exclusive access by the particular compute node.

Global shared memory subsystem

An embodiment of the present invention is directed to a system for distributing an application environment to a compute node. The system includes a first storage unit for storing blocks of a root image of the compute node and a second storage unit for storing a leaf image comprising new data blocks and changes to the blocks of the root image. The system further includes a union block device for interfacing between the compute node and the first and second storage units to distribute the application environment to the compute node. The union block device creates the application environment by merging the blocks of the root image stored on the first storage unit with the leaf image stored on the second storage unit.

Block-level I/O subsystem for distributed application environment management

Present invention unity parallel processing systems and methods facilitate flexible utilization of sequential program applications in a distributed multi-computer parallel processing environment. The new unity parallel processing architecture enables multiple processing nodes (e.g., SMPs) to perform multi-thread processing within the multiple processing nodes while providing a shared virtual global memory space. Symmetric multiprocessors run shared memory applications with modified runtime guidance directives that permit the memories to emulate a virtual global memory across the plurality of symmetric multiprocessors. Within each SMP node, programs utilize multiple threads according to directives and library calls. Across multiple SMP nodes, each SMP node is treated as a single process with one-way communication to other SMP nodes. Portions of the program data are stored in memories associated with the SMP nodes and communication of the program data across multiple SMP nodes is controlled by unity compiler directives.

Unity parallel processing system and method

Methods and systems for processing data communicated over a network. In one aspect, an exemplary embodiment includes processing a first group of network packets in a first processor which executes a first network protocol stack, where the first group of network packets are communicated through a first network interface port, and processing a second group of network packets in a second processor which executes a second network protocol stack, where the second group of network packets is communicated through the first network interface port. Other methods and systems are also described.

Methods and systems for processing network data

A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall ('flush') command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Multi-processor computer system with cache-flushing system using memory recall

A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

Multi-processor computer system with transactional memory

A cache coherent distributed shared memory multi-processor computer system is provided with a cache-flushing engine which allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the cache-flushing engine, a 'flush' command is issued which forces the owner cache to write-back the dirty cache line to be flushed. Subsequently, a 'flush request' is issued to the home memory of the memory block. The home node will acknowledge when the home memory is successfully updated. The cache-flushing engine operation will be interrupted when all flush requests are complete.

Cache-flushing engine for distributed shared memory multi-processor computer systems

A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.

Multi-processor computer system with lock driven cache-flushing system

A system and method for processing multiple main memory accesses in parallel includes transmitting from the processor to the system control unit a first and a second transaction. These transactions are decoded to determine their corresponding commands and addresses. The system control unit includes a qualifier and a scheduler that assigns each transaction to a particular finite state machine (FSM). Each FSM executes a single transaction until completed. Each FSM machine maintains a record or keeps track of the state of progress of a transaction that is being executed by the system control unit. The FSMs keep track of the data by storing the data, such as the current state of the transaction, the status of the data, and an identifier describing which processor issued the transaction, for each transaction in a data buffer. The data value corresponding to a particular transaction may be retrieved from the main memory using a FSM. Since a different FSM is used to retrieve data values, the execution of these transactions can be performed in parallel. Parallel processing of memory accesses using FSMs enhances the speed and efficiency of computer systems.

System and method for tracking and processing parallel coherent memory accesses

Systems and methods of processing network packets are described. These systems and methods provide improved packet processing results by logically and physically separating packet header processing functions from packet data processing functions. In this way, a network processing system may perform network handling operations and data processing operations substantially in parallel. One or more embodiments feature a network adapter for exchanging with a computer network information in the form of packets each including a packet header and packet data. The network adapter includes a packet parser configured to parse an information packet into a packet header and packet data and to direct the packet header to a first memory address for protocol processing and to direct packet data to a second memory address for data processing.

Growing community of inventors

Cupertino, CA, United States of America

Tung M Nguyen