Taiwan Semiconductor Manufacturing Comp. Ltd.

Tung-I Lin

Yeur-Luen Tu

Yu-Hung Cheng

Wei-Li Chen

Cheng-Ta Wu

Chia-Shiung Tsai

Ru-Liang Lee

Cheng-Lung Wu

Ching-Wei Tsai

Alexander Kalnitsky

Shih-Pei Chou

Jhy-Jyi Sze

Shyh-Fann Ting

Tung-Hsiung Tseng

Ching-Pei Su

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

Semiconductor structure having a silicon active layer formed over a SiGe etch stop layer and an insulating layer with a through silicon via (TSV) passed therethrough

A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

Semiconductor wafer with low defect count and method for manufacturing thereof

Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween

A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

Method of forming source/drain regions of transistors

Transistor channel

Backside illuminated (BSI) image sensor devices are described as having pixel isolation structures formed on a sacrificial substrate. A photolayer is epitaxially grown over the pixel isolation structures. Radiation-detecting regions are formed in the photolayer adjacent to the pixel isolation structures. The pixel isolation structures include a dielectric material. The radiation-detecting regions include photodiodes. A backside surface of the BSI image sensor device is produced by planarized removal of the sacrificial substrate to physically expose the pixel isolation structures or at least optically expose the photolayer.

Pixel isolation device and fabrication method

Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.

Deep trench isolation structure and method of forming same

A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

The present disclosure provides a method of manufacturing an image sensor device. The method includes: forming an etch stop layer on a first substrate; forming a light-sensing region comprising a light sensing quantum structure being able to detect a wavelength greater than about 1.5 um; forming a semiconductive substrate over the light-sensing region, the semiconductive substrate comprising an active component; forming an isolation structure extended through the light-sensing region; selectively removing the first substrate to expose the etch stop layer; and thinning the etch stop layer thereby exposing the light-sensing region.

Image sensor device and manufacturing method thereof

A method for manufacturing a deep trench isolation (DTI) structure with a tri-layer passivation layer is provided. An etch is performed into a semiconductor substrate to form a trench. A first undoped semiconductor layer is formed by epitaxy lining surfaces of the semiconductor substrate that define the trench. A doped semiconductor layer is formed by epitaxy over and lining the first undoped semiconductor layer in the trench. A second undoped semiconductor layer is formed by epitaxy over and lining the doped semiconductor layer in the trench. A structure resulting from the method is also provided.

Deep trench isolation (DTI) structure with a tri-layer passivation layer

A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

Semiconductor device with trench isolation

The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Transistor with performance boost by epitaxial layer

The present disclosure provides a complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device. In accordance with some embodiments, the device includes a semiconductor region having a front surface and a back surface; a light-sensing region extending from the front surface towards the back surface within the semiconductor region; a gate stack formed over the semiconductor region; and at least one epitaxial passivation layer disposed at least one of over and below the light-sensing region. In some embodiments, the at least one epitaxial passivation layer includes a p-type doped silicon (Si) layer.

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Tainan, Taiwan

Tung-I Lin