Taiwan Semiconductor Manufacturing Comp. Ltd.

Tung-Chin Yeh

Liang-Chen Lin

Jyun-Lin Wu

Gia-Her Lu

Hsien-Pin Hu

Shih-Kai Lin

Shih-Cheng Chang

Fu-Tsai Hou

Tung-Jiun Wu

An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors

A semiconductor package structure includes a semiconductor substrate including a plurality of through substrate vias (TSV) extending from a first surface to a second surface of the semiconductor substrate, wherein the second surface is opposite to the first surface; a plurality of conductive bumps on the second surface and connected to a corresponding TSV; a polymeric layer on the second surface and surrounding a lower portion of a corresponding conductive bump. The polymeric layer includes a first portion configured as a blanket covering a periphery region of the semiconductor substrate; and a second portion in a core region of the semiconductor substrate and configured as a plurality of isolated belts, wherein each of the isolated belts surrounds a corresponding conductive bump.

Semiconductor package structure with polymeric layer and manufacturing method thereof

Methods for forming stacked capacitors with fuse protection

Growing community of inventors

Toufen, Taiwan

Tung-Chin Yeh