Synopsys, Inc.

Synopsys Taiwan Co., Ltd.

Springsoft, Inc.

Springsoft Usa, Inc.

Mediatek Corporation

Tung-Chieh Chen

Sheng-Hsiung Chen

Yao-Wen Chang

Fong-Yuan Chang

Hung-Ming Chen

Wai-Kei Mak

Ren-Song Tsay

Chien-Hung Lu

Po-Hsun Wu

Po-Hung Lin

Tsung-Yi Ho

Yi-Peng Weng

Meng-Kai Hsu

Tien-Yueh Liu

Shyh-Chang Lin

Hsin-I Lin

Chun-Cheng Chi

Po-Cheng Pan

Jui-Hsiang Liu

Ping-Hung Yu

Fwu-Juh Huang

Chun-Chen Chi

Bo-Wei Chen

Ta-Yu Kuan

Kai-Chih Chi

Che-Wei Jiang

Ching-Yu Chin

A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Knowledge-based analog layout generator

A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.

Spine routing and pin grouping with multiple main spines

A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.

Efficient analog layout prototyping by layout reuse with routing preservation

Spine routing with multiple main spines

A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.

Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratios

A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.

Switch cell

A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.

Method of fast analog layout migration

A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the 'H/V Demand Ratio.' From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio

A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

Method of packing-based macro placement and semiconductor chip using the same

A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints.

Disclosed is a computer-implemented method to generate a placement for a plurality of device modules within an analog integrated circuit (IC) subject to a set of constraints. By building a constraint hierarchy tree according to the constraints, conflicts of constraints can be identified and resolved. Furthermore, placements can be generated based on the hierarchy tree through a bottom-to-top dimension optimization process and a top-down wire length optimization process. Furthermore, a graphical user interface can be used to display the tree, and the user can edit the tree visually and interactively.

Method of constraint-hierarchy-driven IC placement

A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement.

Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit

A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC. The placer iteratively repeats the declusterization and routability improvement process until the global placement plan specifies positions of all blocks residing at the lowest level of the hierarchy, with weighting of the bin density term adjusted when necessary during each iteration of the routability improvement process to provide sufficient white space in each bin. The placer employs a look-ahead legalization technique to move low level blocks to legal positions during later iterations of the plan improvement process.

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Taipei, Taiwan

Tung-Chieh Chen