Macronix International Co., Ltd.

Ememory Technology Inc.

Powerflash Technology Corporation

Tung-Cheng Kuo

Chien-Hung Liu

Shyi-Shuh Pan

Shou-Wei Huang

Hsiang-Lan Lung

Shue-Shuen Chen

Shou-Wei Hung

Shou-Wei Hwang

Hsin-Ming Chen

Ching-Sung Yang

Meng-Yi Wu

Chia-Hsing Chen

Cheng-Jye Liu

Chih-Hao Huang

Lun-Chun Chen

Samuel Cheng-Sheng Pan

Sheng-Kai Chen

Ruei-Ling Lin

A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

Semiconductor apparatus with fake functionality

An integrated circuit design protecting device includes a switch device and a non-volatile memory. The switch device includes M input ports, N output ports, N multiplexers, and S selection nodes. Each multiplexer of the N multiplexers includes I input nodes, an output node, and at least one selection node. The I input nodes are coupled to I input ports of the M input ports. The output node is coupled to an output port of the N output ports. The non-volatile memory is coupled to the S selection nodes of the switch device for providing selection codes to the switch device.

Integrated circuit design protecting device and method thereof

The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code.

Mobile phone accessing system and related storage device

A structure and operating method for a nonvolatile memory cell. First and second bit lines are disposed on a substrate. A channel is disposed between the first and second bit lines in an active area. First and second selective gates are disposed on the first and second bit lines respectively. An isolation structure is disposed between the first bit line and the first selective gate and between the second bit line and the second selective gate. A control gate is disposed over the first and second selective gates and the channel. An oxide-nitride-oxide (ONO) layer is disposed between the first and second selective gates and the control gate and between the channel and the control gate.

Structure and operating method for nonvolatile memory cell

A method for fabricating an embedded flash ROM structure having code cells and data cells. A substrate is provided and then a plurality of bit lines are formed over the substrate. A plurality of isolation structures are formed over the bit lines and a charge trapping layer is formed between the isolation structures. A plurality of word lines are formed over the isolation structures and the charge trapping layer to form the embedded flash ROM structure. According to requirement, embedded flash ROM structure is divided into a code cell region and a data cell region.

Method for fabricating embedded flash ROM structure having code cells and data cells and operations for the same

An ultraviolet-programmable P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell to be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

UV-programmable P-type mask ROM

A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer and a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Non-volatile memory device and fabrication method thereof

A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

Non-volatile memory capable of preventing antenna effect and fabrication thereof

A fabrication method for lines of a semiconductor device provides a substrate with a deposition layer already formed thereon, followed by forming a photoresist layer on the deposition layer. Photolithography is conducted with a mask to pattern the photoresist layer, wherein the photoresist layer is designed with the consideration of both the proximity effect and the microloading effect due to etching. Thereafter, using the patterned photoresist layer as an etching mask, an etching is conducted to form a plurality of lines. Since during the patterning of the photoresist layer, the proximity effect and the microlaoding effect are being considered, the difference in the linewidths between the dense feature region and the scattered feature region is minimized after the etching process.

Fabrication method for lines of semiconductor device

A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.

Non-volatile memory

The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.

Non volatile embedded memory with poly protection layer

A method for operating a non-volatile memory with symmetrical dual-channels. A programmed step is performed on the non-volatile memory to retain charges in both sides of an ONO layer so that the symmetrical dual-channels are generated and the one-bit writing step is completed. Afterwards, a selected voltage is simultaneously exerted on a first bit line and a third bit line to select a second bit line of the symmetrical dual-channels. Finally, a reading voltage is applied to the second bit line to acquire a reading current which is the sum of total current through the symmetrical dual-channels for increasing the reading speed of the non-volatile memory.

Method for operating non-volatile memory with symmetrical dual-channels

A method for fabricating a Mask ROM is described, in which an ONO composite layer and a plurality of gate structures are formed on a substrate. A plurality of bit-lines are formed in the substrate between the gate structures and a plurality of word-lines are formed over the substrate to electrically connect with the gate structures. A chemical vapor deposition anti-reflective coating (CVD-ARC) with coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer not covered by the CVD-ARC. A plurality of plugs are then formed in the coding windows.

Mask read-only memory and fabrication thereof

A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

A method for fabricating an UV-programmed P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

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Yilan Hsien, Taiwan

Tung-Cheng Kuo