Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Tung-Cheng Chang

Yih Wang

Gu-Huan Li

Chun-Ying Lee

Perng-Fei Yuh

Chia-En Huang

Meng-Sheng Chang

Chia-en Huang

Meng-Fan Chang

Ku-Feng Lin

Yu-Fan Lin

Jimmy Lee

A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

Memory devices with dual-side access circuits and methods for operating the same

A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Memory device and operating method of the same

A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Semiconductor memory devices with diode-connected MOS

A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Memory circuits and devices, and methods thereof

One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

Multiple stack high voltage circuit for memory

A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N N MOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle.

Growing community of inventors

Miaoli County, Taiwan

Tung-Cheng Chang