Realtek Semiconductor Inc.

Tung-Chen Kuo

Ming-Chun Chang

Kuen-Bin Lai

Disclosed is an adjusting circuit for determining a target delay clock signal of a delay circuit having a plurality of delay units. The delay circuit generates a plurality of delay clock signals, and the adjusting circuit includes: a difference signal generating circuit, for generating a plurality of difference signals according to a reference clock signal and the delay clock signals; a delay processing circuit, coupled to the difference signal generating circuit, for determining the target delay clock signal by computing a corresponding number of delay units for a specific phase of the reference clock signal according to the difference signals; wherein the target delay clock signal is one of the delay clock signals.

Adjusting circuit and method for delay circuit

Disclosed is a data reading circuit, including: a first register, for receiving a first data signal and generating a second data signal by sampling the first data signal via the first edge of a first predetermined signal; a second register, for sampling a second data signal by the second edge of a second predetermined signal to generate a third data signal; a first selector, for selecting one of the second and third data signals as a fourth data signal according to the phase difference between the first and second predetermined signals; a second selector, for selecting one of the fourth and a fifth data signals as a sixth data signal according to a selecting signal; and a third register, for sampling the sixth data signal to form the fifth data signal according to the first edge of the second predetermined signal.

Data reading circuit

A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock signal to generate sampled values; first memory units, wherein the first memory units are utilized to memorize the sampled values, and each of first memory unit outputs at least one of the sampled values according to a corresponding first selecting signal; a first selecting unit, for outputting the sampled values according to a second selecting signal; a determining module, for determining if the sampled values meet a specific relation, where if the determination result is positive then determining the particular delaying stage; and a counter for generating a counting value to control the delayed clock signal sampled by the first register.

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Hsin-Chu, Taiwan

Tung-Chen Kuo