Cadence Design Systems, Inc.

Tulio Paschoalin Leao

Matheus Nogueira Fonseca

Artur Melo Mota Costa

Guilherme Seminotti Braga

Rodrigo Fonseca Rocha Soares

Alberto Manuel Arias Drake

Lucas Martins Chaves

Paula Selegato Mathias

Tales Bontempo Cunha

Petros Daniel Fernandes De Medeiros Félix

Julia Pinheiro De Oliveira

Arthur Ribeiro Araujo

Gabriel Guedes De Azevedo Barbosa

Rogério De Souza Moraes

Andrei Dos Santos Silva

Pablo Nunes Agra Belmonte

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.

Systems and methods for command interpretation in an electronic design automation environment

A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.

Formal verification with EDA application and hardware prototyping platform

The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using at least one processor, an electronic design and isolating a combinational loop associated with the electronic design. Embodiments may further include inserting a sequential element in a loop path of the combinational loop, wherein the sequential element has a clock that is at least twice as fast as a fastest system clock associated with the electronic design. Embodiments may also include generating a property that determines whether an input and an output of the sequential element is never different and determining whether the property is true using formal verification.

System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design

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Betim, Brazil

Tulio Paschoalin Leao