Texas Instruments Corporation

Tuli Luthuli Dake

Erhan Ozalevli

Mustapha El Markhi

Satish Kumar Vemuri

Gianpaolo Lisi

Jingwei Xu

Rohit Bhan

Dingkun Du

Laszlo Balogh

Ritesh Jitendra Oza

A driver includes a first pre-driver having a first drive strength programming input and a first output, a first transistor having a first transistor control input coupled to the first output, and a second pre-driver having a second drive strength programming input and a second output. The driver also includes a second transistor having a second transistor control input coupled to the second output. The second transistor is coupled to the first transistor and to a driver output terminal. A circuit is coupled between the driver output terminal and the first drive strength programming input and between the driver output terminal and the second drive strength programming input.

Driver with adaptive drive strength

Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Floating high-voltage level translator with adaptive bypass circuit

A driver includes first and second switches. A first transistor has a first control input and first and second current terminals. A resistor couples between a voltage supply terminal and the first control input. A configurable voltage clamp circuit has a voltage clamp control input and a voltage clamp circuit output coupled to the first control input. A second transistor has a second control input and third and fourth current terminals. A logic circuit includes a comparator having a comparator output. The logic circuit couples to the voltage supply terminal and the voltage clamp control input. The logic circuit is configured to configure the voltage clamp circuit for a first clamp voltage at the voltage clamp circuit output responsive to the first switch being turned ON and for a second clamp voltage at the voltage clamp circuit output based on a signal at the comparator output.

Driver discharge circuit

An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

Battery charging and measurement circuit

An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Wide high voltage swing input comparator stage with matching overdrive

A wireless power transfer system using a resonant rectifier circuit with capacitor sensing. A wireless power transfer system includes a power receiver resonant circuit and a synchronous rectifier. The power receiver resonant circuit includes an inductor and a capacitor connected in series with the inductor. The synchronous rectifier is configured to identify zero crossings of alternating current flowing through the inductor based on voltage across the capacitor, and control synchronous rectification of the alternating current based on timing of the zero crossings.

Resonant rectifier circuit with capacitor sensing

One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.

Phase-locked loop (PLL) circuit

In a described example, an apparatus includes: transistor having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a gate terminal; a temperature sensor configured to sense a junction temperature of the transistor and generate a temperature signal based on the sensed junction temperature; and a gate driver circuit configured to generate a gate signal based on the temperature signal and to output the gate signal to the gate terminal of the transistor.

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Plano, TX, United States of America

Tuli Luthuli Dake