International Business Machines Corporation

Tuhin Mahmud

Charles Jay Alpert

Stephen Thomas Quay

Zhuo Li

Chin Ngai Sze

Yaoguang Wei

Eric Jason Fluhr

Robert Mahlon Averill, Iii

Jose L P Neves

Arvind K Karandikar

Lakshmi Narasimha Reddy

Joachim Gerhard Clabes

Saiful Islam

Abraham Mathews

Bryan Glen Hickerson

Divya Kumudprakash Joshi

Geoffrey Wang

Erica Stuecheli

John Reysa

Brian Kozitza

Mohamed Baker Alawieh

Glenn R Bee

Paul G Villarrubla

Aspects of the invention include obtaining one or more feature values that define an architecture design of a memory array and implementing a machine learning model to obtain a predicted power, performance, and area (PPA) of the memory array based on the one or more features. The predicted PPA output by the machine leaning model is assessed based on predefined PPA goals. A design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.

Integrated circuit development using machine learning-based prediction of power, performance, and area

Methods, systems and computer program products for clustering simulation failures are provided. Aspects include receiving simulation data comprising a plurality of simulation failure files, generating a token for each simulation failure file of the plurality of simulation failure files, determining a token score for each token for each simulation failure file of the plurality simulation failure files, normalizing each token score for each token in the plurality of simulation failure files utilizing a weighting scheme to create a normalized token score for each token, determining a set of groups for the plurality of simulation failure files, and assigning one or more simulation failure files from the plurality of simulation failure files into a group in the set of groups based at least in part on normalized token score.

Clustering simulation failures for triage and debugging

Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Automatic generation of wire tag lists for a metal stack

A system, process, etc. according to some embodiments, which includes operations that include selecting one of a plurality of solutions ('selected solution') for optimization of an integrated circuit design during physical synthesis. The operations can further include performing on the selected solution a fast evaluation of a specific metric without updating design documents (e.g., without updating a netlist or metric map). If the evaluation of the specific metric is non-satisfactory, then the candidate solution is rejected. If the evaluation of the specific metric is satisfactory, then a design document is updated and a full evaluation of the specific metric (and other metrics) can be performed.

Physical synthesis optimization with fast metric check

A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.

Resolving global coupling timing and slew violations for buffer-dominated designs

A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or 'wires' are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the 'slack' gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.

Concurrent buffering and layer assignment in integrated circuit layout

A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.

Slew constrained minimum cost buffering

Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.

Buffer insertion to reduce wirelength in VLSI circuits

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Tuhin Mahmud