Analog Devices,inc.

Analog Devices Global

Tudor M Vinereanu

Colin Gerard Lyden

Dennis A Dempsey

Thomas G O'Dwyer

Dermot G O'Keeffe

Oliver James Brennan

Alan Walsh

Eoin Edward English

Mark Murphy

Denis Martin O'Connor

Patrick C Kirby

Donal Bourke

Javier Calpe-Maravilla

Sean B Brennan

Gavin Patrick Cosgrave

Roderick McLachlan

Donal P Geraghty

Albert C O'Grady

Liam Patrick Riordan

Camille Louis Huin

Alan Patrick Cahill

Paul Vincent Errico

Alan Cahill

Helen Stapleton

David Harty

Subject matter herein can include identifying a biochemical test strip assembly electrically, such as using the same test circuitry as can be used to perform an electrochemical measurement, without requiring use of optical techniques. The identification can include using information about a measured susceptance of an identification feature included as a portion of the test strip assembly. The identification can be used by test circuitry to select test parameters or calibration values, or to select an appropriate test protocol for the type of test strip coupled to the test circuitry. The identification can be used by the test circuitry to validate or reject a test strip assembly, such as to inhibit use of test strips that fail meet one or more specified criteria.

Susceptance measurement for identifying biochemical sensors

Embodiments of the present invention provide a motor-driven mechanical system with a detection system to measure properties of a back channel and derive oscillatory characteristics of the mechanical system. Uses of the detection system may include calculating the resonant frequency of the mechanical system and a threshold drive Drequired to move the mechanical system from the starting mechanical stop position. System manufacturers often do not know the resonant frequency and Dof their mechanical systems precisely. Therefore, the calculation of the specific mechanical system's resonant frequency and Drather than depending on the manufacturer's expected values improves precision in the mechanical system use. The backchannel calculations may be used either to replace or to improve corresponding pre-programmed values.

Control techniques for motor driven systems

A digital sine wave may be converted to an analog signal at a digital to analog converter (DAC). The converted analog signal may be supplied to a device and an analog return signal from the device may be passed through a relaxed anti-aliasing filter and converted to digital code words at an analog to digital converter (ADC). An impedance may be calculated from the results of a Fourier analysis of the digital code words. The ADC and DAC clock frequencies may be asynchronous, independently variable, and have a greatest common factor of 1. The clock frequencies of the ADC and/or DAC may be adjusted to change a location of images in the ADC spectrum. By using these different, adjustable clock frequencies for the ADC and the DAC, an analog signal may have increased aliasing without introducing signal errors at a frequency of interest.

Impedance measurement device and method

A method to adjust a waveform transmitted from a field device to overcome cable bandwidth limitations by passing data to be transmitted through a channel compensation device which pre-distorts data to be transmitted to compensate for the bandwidth limitations. The predistortion may make sure that there is a good quality signal received at the control end of the cable.

Method and apparatus for equalizing a transmit channel for cable losses in a C8PSK HART system

The present invention relates to a system and method for digitally compensating signal converters and in particular a digital to analog converter which receives digital input data for a digital to analog converter and supplies anti-function digital coefficients derived from the error function of the digital to analog converter and corresponding to the digital input data and applies the anti-function digital coefficients to the digital input data to pre-condition the digital input data to compensate for the error function of the digital to analog converter. The invention also extends to analog to digital converters.

System and method for digital compensation of digital to analog and analog to digital converters

The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

Digital to analog converter with shared calibration

A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Digital-to-analog converter structures

An integrated digital calibration circuit and digital to analog converter includes a digital to analog converter (DAC) and a digital calibration circuit including a memory for storing predetermined end point coefficients of the digital to analog converter transfer function; and an arithmetic logic unit for applying the end point coefficients to the DAC input signal to adjust the end points of the DAC and/or analog signal chain.

Integrated digital calibration circuit and digital to analog converter (DAC)

A signal generator () for generating a square waveform analog voltage output signal comprises an on-chip DAC () which outputs the analog voltage signal on an output terminal (). On-chip first and second programmable registers () store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit () selectively and alternately switches the first and second registers () to an on-chip DAC register () from which the respective first and second digital words are loaded into the DAC () in response to a load DAC signal generated by a control circuit (). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (). A flip-flop () in response to the load DAC signal outputs a control signal on a control line () for alternately switching the first and second registers () to the DAC register (). The frequency of the analog output signal is determined by the frequency of the LDAC signal, and is half the frequency of the LDAC signal.

Signal generation using DAC having selectively switched registers storing output values

A method for communicating between a controller and a device with double-buffered inputs comprises the steps of providing one or more communication paths for exchanging data between the controller and the device, providing a data transfer control signal from the controller to the device for transferring input data from one or more input registers into one or more latchable data registers, and providing a data transfer delay signal from the device to the controller, wherein, in a first logic state, the data transfer delay signal prevents transfer of input data from the input registers into the latchable data registers until after a transition to a second logic state occurs on the data transfer delay signal. An apparatus for communicating between a controller and a device is also described.

Growing community of inventors

Cork, Ireland

Tudor M Vinereanu