Intel Corporation

Marvell International Limited

Tuan X Do

Lawrence T Clark

Eric J Hoffman

Vikas R Amrelia

Raphael A Soetan

John K Schwartzlow

An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Tap connections for circuits with leakage suppression capability

The present invention discloses a method and apparatus for testing a memory array. The memory array includes a plurality of memory blocks. A test data item is written to the memory blocks at a pre-determined location in parallel. The data from the memory blocks are read at the pre-determined location in parallel. These data items are compared to determine if they are identical. One of these data items is compared with the test data item.

Parallel access testing of a memory array

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Chandler, AZ, United States of America

Tuan X Do