Vtc Inc.

Texas Instruments Corporation

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Tuan V Ngo

Craig Matthew Brannon

Raymond Elijah Barnett

Raymond E Barnett

John D Leighton

John J Price, Jr

Scott Gary Sorenson

Richard E Hester

Douglas R Peterson

Jeremy Robert Kuehlwein

Bryan E Bloodworth

Douglas Warren Dean

Marius Vicentiu Dina

John S Shier

Glenn C Mayfield

Thomas Cougar VanEaton

One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in response to an input signal. The driver circuit also comprises at least one programmable variable resistor configured to provide a bias magnitude of the output transistor that sets a power of the driver circuit to be commensurate with a data-rate of the input signal.

Driver with programmable power commensurate with data-rate

One embodiment of the invention includes an amplifier system. The amplifier system comprises an amplifier stage configured to receive an input signal at an amplifier input and to provide an amplified output signal. The amplifier system also comprises a programmable input impedance stage comprising a plurality of transconductance stages. At least one of the plurality of transconductance stages can be selectively activated based on a selection signal, the at least one of the activated transconductance stages providing current through the amplifier input that adjusts an impedance associated with the amplifier input based on the amplified output signal.

Amplifier with programmable input impedance

A circuit () for use in a mass data storage device () has first () second () current driver circuits for providing write currents to the data transducer (). The first and second current levels are different, the second current level being lower than the first. The first current driver circuit () may be used to apply currents representing user data to the data transducer () and the second current driver circuit () may be used to apply currents representing servo information to the data transducer (). In addition, the first () and second () current drivers circuits may be operated at different frequencies. The first () and second () current driver circuits additionally may share at least some circuit components (--), and may operate at different write speeds.

Low power servo mode write driver

An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first write signal and a second write signal; includes: (a) a directing circuit receiving the write signals, directing a current to establish a voltage across the write head in a first excursion toward a first polarity in response to the first write signal and directing the current to establish the voltage across the write head in a second excursion toward a second polarity substantially opposite the first polarity in response to the second write signal; (b) a first boost system coupled with the directing circuit and boosting the write voltage toward the first polarity during the first excursion; and (c) a second boost system coupled with the directing circuit and boosting the write voltage toward the second polarity during the second excursion.

Apparatus and method for applying write signals for driving a write head

The present invention describes a voltage-mode boosting write driver circuit (), comprising a plurality of inputs (WDP, WDN), a plurality of outputs (HWX, HWY), a transducer (L), a flex interconnection (T) coupled to the outputs (HWX, HWY) and to the transducer (L), a first resistor (R) and a second resistor (R) coupled to the outputs (HWX, HWY) and to the transducer (L), an H-switch (Q, Q, Q, Q) coupled to the resistors (R, R), and a plurality of top boosting circuits (Q, Q, R, and Q, Q, R) coupled to the outputs (HWX, HWY).

Write driver with continuous impedance match and improved common mode symmetry

An apparatus for applying write signals including a first write signal and a second write signal to write information to a memory device includes a current directing circuit receiving the write signals and directing a write current to establish a write voltage between first and second write loci in a first or second excursion toward a first or second polarity in response to the first or second write signal. The first and second write loci are coupled with supply locus via an adjacent first or second impedance unit and a first or second switching unit. The first and second switching units are controlled at first and second control loci by the first and second write signals. First and second boost systems are coupled with the first and second control loci for boosting the write voltage toward the first and second polarities during first and second excursions.

A preamplifier device () for a thin film transducer disk drive system having operation speeds up to and greater than 2 Gb/s. The device () includes a low power/high speed driver () having a cascaded Class AB buffer. In at least one embodiment the device () includes separated drive devices in the driver () and H-bridge circuit () realized in multiple smaller devices biased separately to reduce transistor self-heating effects and a further embodiment includes a reference () having a base cancellation scheme and a Class AB current source for improving accuracy and stability is such high speed devices.

High speed pre-driver with voltage reference for thin film head write driver

A write driveris implemented to provide near-ground common mode output voltages to produce a more symmetrical head voltage swing (i.e. &#xb1;0.4V from ground to &#xb1;5V supply voltages). These features help to reduce the effects of common mode impedance associated with the interconnection to the disk drive head to improve overall performance. Lower jitter at high data rates can be achieved when compared to prior art techniques for implementing current mode write drivers. Further, the matched impedance between the write driverand the interconnectioneliminates unwanted reflections. ECL level voltage swings (200&#x2013;500 mV) have replaced more conventional CMOS level voltage swings (5V) to further reduce overall power dissipation associated with the write driver. The small ECL level switching further maintains constant power dissipation with changes in operating frequency and results in less NTLS effects due to quieter supplies.

Circuit and method to match common mode flex impedance and to achieve symmetrical switching voltage outputs of write driver

A system and method provide overshoot protection to facilitate driving a load by output circuitry in response to a transition from a first operating mode to a second operating mode. The overshoot protection occurs by masking an input bias from biasing the output circuitry for an initial part of the second operating mode based on a transition to the second operating mode, and then allowing the input bias to bias the output circuitry in a desired manner in a subsequent part of the second operating mode.

Power efficient overshoot protection during an operating mode transition

A voltage-mode boosting write driver circuit () having a pair of voltage boosting PMOS transistor sets () coupled to a high current H-switch (). One set () of the boosting PMOS transistors correspondingly pulls output pin HY high, while the other transistor set () correspondingly pulls output pin HX high and the other output pin HY low thereby significantly improving the head voltage swing, and also achieving a faster slew rate. Moreover, resistors (R, R) of the H-switch are both matched to each other and impedance matched to a flex cable (T) interconnection impedance, which interconnection is coupled to the thin film head, to thereby eliminate signal reflection such that the write current (Iw) settles quickly with minimum ringing to achieve a high data rate. Moreover, less power dissipation and smaller number of devices used are achieved by making use of existing transient currents of the pre-driver emitter follower stage.

Method to increase head voltage swing and to reduce the rise time of write driver

A write current circuit ( ) adapted to drive a thin film write head (L ) of a mass media information storage device. The write current circuit includes a write current reference voltage circuit ( ) adapted to selectively establish amplitude of a write current signal. The write current circuit further includes programming circuitry (M -M ) driven such that several parameters of the write current waveform can be controlled, including the write current amplitude, overshoot amplitude and overshoot duration. The present invention achieves technical advantages by providing the ability to both produce an accurate write current, and also providing the ability to establish the write current waveform shape so that customers can optimize disk drive performance even when using different thin film write heads available from different suppliers.

Reference circuit for write driver circuit with programmable write current, overshoot duration and overshoot amplitude control

A write drive circuit ( ) for a hard disk drive selectively providing a current mode operation for high speed data write of a single channel, and selectively providing a voltage mode operation during a servo write operation. A central buffer has a first circuit ( ) providing a current mode drive signal to a head during a single channel write operation, and a second circuit ( ) providing a voltage mode drive signal for multi-channel servo write operation. The outputs of both circuits ( ) is provided over a common differential connection (T ) feeding a pre-driver circuit ( ) adapted to drive one or many heads, as determined by head select control lines ( ). The circuit provides >1.6 Gb/s data write speed in single channel write operation, and has an architecture utilizing only two signal lines for four channels.

Method to write servo on multi-channels with voltage mode data and single channel with current mode data

A write circuit selectively provides a write current through a write head in first and second opposite directions. The write circuit is connected to the write head by an interconnect, and has a positive supply level and a negative supply level. A first voltage source provides a first control voltage, and a second voltage source provides a second control voltage. A first resistor is provided between the first voltage source and the interconnect for impedance matching to the interconnect, and a second resistor is provided between the second voltage source and the interconnect for impedance matching to the interconnect. The first and second control voltages provide a transient voltage to the interconnect and provide a subsequent steady-state voltage to the interconnect.

Impedance-matched write circuit

A read system for reading information from a storage medium and for providing an output signal to circuitry external from the read system is disclosed. The read system includes individual channel circuitry, a bias current generator for providing a bias current to the read system, and preamplifier circuitry connected between the bias current generator and the individual channel circuitry. The individual channel circuitry further includes a first and a second magnetoresistive element, a first and a second transistor, and a first and a second switch. The preamplifier circuit further includes a first and a second capacitor connected between a low potential and the first and second switches, respectively, and a third capacitor connected between the first and second capacitors. The preamplifier also includes a first and a second operational amplifier having an output connected to a base of the first transistor and a base of the second transistor. respectively, and a feedback unit connected to the bias current generator.

Current bias, current sense preamplifier for a magnetoresistive reader

An impedance matching circuit for a write driver matches the differential impedance of the winding of the write head and the transmission line to the write head. The impedance matching circuit includes a resistor connected between a node and a current switch of the write driver. The resistor has an impedance value matching the differential impedance value of the transmission line and head. During quiescent or steady state operation, the write driver provides a DC write current in a selected direction through the winding, and the resistor matches the differential impedance of the head and transmission line. During switching to reverse direction of write current through the winding, however, the resistor dampens voltage swings at the node to minimize current undershoot. Optionally, a capacitor is in parallel with the resistor to short-circuit the resistor during switching to improve the rise-time characteristics of the current reversal, but at a sacrifice of the impedance characteristics during switching.

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Eden Prairie, MN, United States of America

Tuan V Ngo