Broadcom Corporation

The Boeing Company

Tuan Hoang

Hongtao Jiang

Nong Fan

Ichiro Fujimori

Lorenzo Longo

Keh-Chee Jen

Ben Tan

Samuel Chu

A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.

System and method for implementing a single chip having a multiple sub-layer PHY

A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.

A system () includes a communication path () and transmits data on a network (). A transmitter () transmits data on the network and a receiver () receives data from the network. A component () in the communication path has a transfer characteristic (C, C, C) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Bit error rate based system and method for optimizing communication system performance

A method and system for evaluating performance of a device by on-chip determination of BER may include establishing and generating PRBS test packets in a closed communication path internally within a physical layer device (PLD) and a remote PLD. A BER for the PLD may be determined from within the PLD based on a comparison of at least a portion of the generated test packets with at least a portion of the generated test packets transmitted over the closed communication path received by the PLD via the closed communication path from the remote PLD. A transmit path of the PLD may be internally coupled to a receive path of the PLD, and a receive path of the PLD may be internally coupled to a transmit path of the PLD. The PLD may be internally configured to operate in an internal optical loopback mode or an internal electrical loopback mode.

System and method for determining on-chip bit error rate (BER) in a communication system

A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer device under test via an optical interface of the verified physical layer device and an optical interface of the physical layer device under test. Alternately, the electrical interface may also be used for testing. A packet generator may transmit test packets over the established closed communication path and at least a portion of the test packets from the physical layer device under test may be received by the verified physical layer device. Subsequently, the verified physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine whether the physical layer device is defective or operational.

System and method for performing on-chip self-testing

A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths&#x2014;a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

On-chip standalone self-test system and method

A test packet generator () within a physical layer device () may generate test packets to be communicated over a closed communication path established within the physical layer device (). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device () may receive at least a portion of the generated test packet. A test packet checker () within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter () within the physical layer device () may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received.

A system and method for detecting speed related defects in an electronic assembly includes application specific integrated circuits (ASICs) designed with registered I/O's to provide true at-speed testing of the electronic assembly. An interconnect test engine and a test access port controller control the generation of a progressive binary patterns. The test engine receives captured data from the other ASICs in response to the binary patterns. The method includes generating binary progressive scan patterns for the output registers of one ASIC that are scanned and captured at the input registers of another ASIC. The test results are stored in a multiple input shift register (MISR) where they can be accessed for examination and diagnostic evaluations.

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Westminster, CA, United States of America

Tuan Hoang