Intel Corporation

Tuan H Bui

Millind Mittal

Benny Eitan

Alexander D Peleg

Larry M Mennemeier

Carole Dulong

Stephen Anthony Fischer

Eiichi Kowashi

Benny Maytal

Michael J Keith

Kevin Harney

Michael Kelly

According to an embodiment of the invention, a processor comprises a register file and a register stack engine. The register file has a predetermined size and a set of registers in the register file is allocated when a function in a code sequence is called. The register stack engine saves the contents of a set of registers in a reserve storage area responsive to a function call if the function call would overflow the predetermined size of the register file. The register stack engine restores data from the reserve storage area to the register file if a recursive function call occurs.

Processor with register stack engine that dynamically spills/fills physical registers to backing store

Microprocessor system and method for increasing memory Bandwidth for data transfers between a cache and main memory utilizing data compression

A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.

System for signal processing using multiply-add operations

A method of multiplying and accumulating two sets of values in a computer system. A packed multiply add is performed on a first portion of a first set of values packed into a first source and a first portion of a second set of values packed into a second source to generate a first result. The first result is unpacked into a plurality of values (e.g. two). The plurality of values is then added together to form a resulting accumulation value.

Method and apparatus for performing multiply and accumulate operations

A system and method is provided for encoding data wherein contiguous data values represent a video image. Three contiguous data values are applied to a loop filter to provide digital filtering of the data values. A frame differencing device performs a subtraction operation upon one of the three contiguous data values simultaneously with the performance of a filtering operation upon another one of the three contiguous data values. Additionally, a discrete cosine transform device performs transform operations upon the third contiguous data value simultaneously with the performance of the digital filtering and the frame differencing operation upon the other two contiguous data values. Because the loop filter is a multipass device the frame differencing device and the discrete cosine transform device must wait while some filtering operations are performed. As soon as one of the contiguous values is applied to the output of the digital filtering device it is operated upon by the frame differencing device. When the frame differencing device is done with this value the discrete cosine transform device begins operating upon the output of the frame differencing device and the frame differencing device operates on the next contiguous data value from the loop filter. A discrete cosine transform system is provided for performing discrete cosine transforms on matrices of input video data.

Pipelined video encoder architecture

A transform coefficient matrix is factorized in two submatrices of coefficients. One submatrix is applied to a subword formed of selected input data points and the other submatrix is applied to a subword formed of other selected input data points. This provides two sets of transformed output words. These transformed output data words are then combined. The two subwords may include, respectively, the odd data points and the even data points of the input data word. Alternately, the two subwords may include the high order data points and the low order data points. The transform performed by these operations may be the forward discrete cosine transform or the inverse discrete cosine transform. The submatrices of coefficients may be applied to differences of data points as well as to sums of data points. The differences and sums of data points may be applied to the submatrices of transform coefficients by the use of respective circular buffers.

Method, apparatus, and system for transforming signals

A signal is encoded by (1) generating a difference signal using a current input signal and a current reference signal, (2) transforming the difference signal to a transform domain, (3) quantizing the transformed signal, and (4) further encoding the quantized signal. The encoded signal is then transmitted, either for storage or for decoding by a remote decoding system. The quantized signal (i.e., without any further encoding) is also dequantized and the resulting dequantized signal is transformed back (i.e., inverse transformed) to the original signal domain as a reference difference signal. The reference difference signal is then added to the current reference signal to generate a next reference signal. The next reference signal may then be used to encode a next input signal. A single transform circuit implements both the forward transform and the inverse transform during encoding by configuring the circuit differently for the forward and inverse transforms.

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Phoenix, AZ, United States of America

Tuan H Bui