Advanced Micro Devices Corporation

Sandisk Technologies Inc.

Sandisk Corporation

Other

Leading Edge Technologies, Inc.

Sony Corporation

Sony Electronics Inc

Pdf Solutions, Incorporated

Prolink, Inc.

Tuan Duc Pham

Mark T Ramsbey

Masaaki Higashitani

Angela Tai Hui

George Matamis

Yu Nan Sun

Jongsun Sel

James K Kai

Takashi Whitney Orimoto

Henry Chien

Sameer S Haddad

Chi K Chang

Vinod Robert Purayath

Jeffrey W Lutze

Jayavel Pachamuthu

Hiroyuki Kinoshita

Kazuya Tokunaga

Yupin K Fong

Richard W Rudow

John R Coffee

Kirk H Bingeman

Marika Gunji-Yoneoka

Douglas L Lecker

Sanghyun Lee

Chan Park

Nima Mokhlesi

Gerrit Jan Hemink

Klaus Florian Schuegraf

Jeffrey Allan Shields

Robert B Ogle

Naoki Takeguchi

Mitsuteru Mushiga

Kensuke Yamaguchi

Jusuke Ogura

Cheng-Chung Chu

Hao Fang Fang

Hidetaka Horiuchi

Eli Harari

Bharath Rangarajan

Michael K Templeton

Henry Chin

Marina V Plat

Mohan Dunga

Timothy J Thurgate

Fumiaki Toyama

Daniel Sobek

Jean Y Yang

Yider Wu

Akio Nishida

Yuan Zhang

Carl Robert Huster

Fumitoshi Ito

Atsushi Suyama

Masaru Yano

Shiqian Shao

Hideki Komori

Kenneth W Au

Daewung Kang

Raghuveer S Makala

Koji Hashimoto

Hiroyuki Ogawa

Rahul Sharangpani

Satoshi Tanaka

Yowjuang William Liu

Lu You

Mark W Randolph

Kikuko Sugimae

Richard J Huang

Yao-Sheng Lee

Kazuhiro Kurihara

Hao Fang

Dawn M Hopper

Seungpil Lee

Effiong Etukudo Ibok

Nicholas H Tripsas

Narbeh Derhacobian

Franz Kreupl

Ravi S Sunkavalli

Masayuki Ichige

Kashmir S Sahota

Michiaki Sano

Lewis N Shen

Kiyohiko Sakakibara

Kwang-Ho Kim

Simon Siu-Sing Chan

Maria Chow Chan

David H Chi

Hiro Kinoshita

Janet S Wang

Hiroaki Iuchi

Shigehisa Inoue

Ryoichi Honma

Masanori Terahara

Shuji Minagawa

Kenneth Wo-Wai Au

Ming Tian

Vincent Shih

Louis Le

Christoph Dolainsky

Tommy C Hsiao

A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.

Non-volatile memory with inter-die connection

An integrated memory assembly comprises a control die bonded to a memory die. The memory die includes multiple non-volatile memory structures (e.g., planes, arrays, groups of blocks, etc.), each comprising a stack of alternating conductive and dielectric layers forming staircases at one or more edges of the non-volatile memory structures. The non-volatile memory structures are positioned with gaps between the non-volatile memory structures such that the gaps separate the staircases of adjacent non-volatile memory structures. Metal interlayer segments positioned in the gaps are connected to a top metal layer positioned above non-volatile memory structures and to one or more electrical circuits on the control die via zero, one or more other metal layers/segments.

Non-volatile memory with efficient signal routing

Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).

Direct memory characterization using periphery transistors

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.

Three-dimensional memory device with through-stack contact via structures and method of making thereof

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, resistive memory elements located in the alternating stack in first and second array regions and contact via structures located in a contact region between the first and the second array regions. The contact via structures have different depths and contact different electrically conductive layers. Support pillars are located in the contact region and extending through the alternating stack. At least one conduction channel area is located between the contact via structures in the contact region. The conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region.

Three-dimensional ReRAM memory device employing replacement word lines and methods of making the same

A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.

Methods and apparatus for three-dimensional nonvolatile memory

Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

Offset backside contact via structures for a three-dimensional memory device

Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof

A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.

Inter-plane offset in backside contact via structures for a three-dimensional memory device

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.

Three-dimensional memory devices having a shaped epitaxial channel portion

Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.

Method of selectively depositing floating gate material in a memory device

In a three dimensional nonvolatile memory, memory holes extend vertically through two or more physical levels in which memory cells are formed. Memory hole structures are formed in memory holes to include vertical channels. Vertical trenches are subsequently formed to divide memory hole structures into two or more vertical NAND strings.

Memory hole structure in three dimensional memory

A method of manufacturing a three-dimensional memory device includes forming, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening, forming an epitaxial channel portion and a memory stack structure in the memory opening, forming a backside contact trench, forming a first backside recess by selectively removing the bottom sacrificial material layer, forming a semiconductor oxide layer underneath the bottom dielectric layer and around a material of the epitaxial channel portion, forming second backside recesses by selectively removing the spacer material layers, and forming electrically conductive layers in the first and second backside recesses.

Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation

A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Triple patterning NAND flash memory

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses.

Blocking oxide in memory opening integration scheme for three-dimensional memory structure

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Santa Clara, CA, United States of America

Tuan Duc Pham