Globalfoundries Singapore Pte. Ltd.

Nanyang Technological University

Tu Pei Chen

Juan Boon Tan

Shyue Seng Tan

Jianxun Sun

Eng Huat Toh

Jian Sun

Chi Yung Ng

A resistive memory device is provided. The resistive memory device comprises a first electrode and a resistive layer over the first electrode, the resistive layer having a sidewall. A second electrode is over the resistive layer. An insulating liner is formed on the sidewall of the resistive layer. The insulating liner comprises two layers of different dielectric materials.

Dual layer dielectric liner for resistive memory devices

A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Memory device and a method for forming the memory device

Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.

Dye-sensitized optoelectronic memory

Disclosed herein is a novel charging controlled RRAM (Resistance Random Access Memory), and various methods of making such a charging controlled RRAM device. In one example, a device disclosed herein includes a first word line structure formed above a substrate, wherein the first word line structure includes a gate electrode and a nano-crystal containing layer of insulating material, a second word line structure formed above the substrate, wherein the second word line structure comprises a gate electrode and a nano-crystal containing layer of insulating material, a first implant region formed in the substrate proximate the first word line structure, wherein the first implant region defines a first bit line, and a second implant region formed in the substrate proximate the second word line structure, wherein the second implant region defines a second bit line.

Charging controlled RRAM device, and methods of making same

A memory structure including a semiconductor substrate, an insulator layer formed on the semiconductor substrate and a gate layer formed on the insulator layer is disclosed. The insulator layer includes a first nanocrystal implanted region proximate to the gate layer and a second nanocrystal implanted region proximate to the semiconductor substrate, wherein the first nanocrystal implanted region has an average nanocrystal concentration which is higher than an average nanocrystal concentration of the second nanocrystal implanted region.

Growing community of inventors

Singapore, Singapore

Tu Pei Chen