International Business Machines Corporation

Tu-An T Nguyen

Dung Q Nguyen

Brian William Thompto

Steven J Battle

Gregory William Alexander

Jeffrey Carl Brownscheidle

Sundeep Chadha

Timothy Carl Bronson

Salma Ayub

Christian Jacobi

Brian David Barrick

Salim Ahmed Shah

Jason D Kohl

Brandon R Goddard

Brendan M Wong

Khandker Nabil Adeeb

Brian D Victor

Balaram Sinharoy

Matthias Klein

Richard James Eickemeyer

Joshua W Bowman

Cliff Kucharski

John Barry Griswell, Jr

Nicholas R Orzol

Winston Herring

Robert J Sonnelitter, Iii

Michael Andrew Blake

Susan Elizabeth Eisen

Albert James Van Norstrand, Jr

David R Terry

Ekaterina M Ambroladze

Deanna Postles Dunn Berger

Michael Joseph Genden

Vesselina K Papazova

Jonathan T Hsieh

Kenneth Lundy Ward

Deepak K Singh

Dhivya Jeganathan

Christopher M Mueller

Glenn Owen Kincaid

Gaurav Mittal

David S Walder

Eula Faye Abalos Tolentino

Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

Castout handling in a distributed cache topology

Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Decentralized hot cache line tracking fairness mechanism

A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

Hot line fairness mechanism favoring software forward progress

A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

Inferring future value for speculative branch resolution in a microprocessor

Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

Preemptive tracking of remote requests for decentralized hot cache line fairness tracking

A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Multiprocessor system cache management with non-authority designation

Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.

Compaction of architected registers in a simultaneous multithreading processor

Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

Inferring future value for speculative branch resolution

Embodiments for fast perfect issue of dependent instructions in a distributed issue queue system. Producer information of a producer instruction is inserted in a lookup entry in a lookup table, the lookup entry being allocated to a register. It is determined that the register corresponding to the lookup entry is a source for a dependent instruction. Responsive to storing the dependent instruction in an issue queue, the producer information is stored in a back-to-back entry of a back-to-back wakeup table, the back-to-back entry corresponding to the dependent instruction. The producer instruction is issued which causes the producer information of the producer instruction to be sent to the back-to-back wakeup table. It is determined that there is a match between the producer information and the back-to-back entry for the dependent instruction, and the dependent instruction is caused to issue based on the match.

Fast perfect issue of dependent instructions in a distributed issue queue system

A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

Finish status reporting for a simultaneous multithreading processor using an instruction completion table

Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Fast multi-width instruction issue in parallel slice processor

A computer data processing system includes a plurality of logical registers, each including multiple storage sections. A processor writes data a storage section based on a dispatched first instruction, and sets a valid bit corresponding to the storage section that receives the data. In response to each subsequent instruction, the processor sets an evictor valid bit indicating a subsequent instruction has written new data to a storage section written by the first instruction, and updates the valid bit to indicate the storage section containing the new written data. A register combination unit generates a combined evictor tag to identify a most recent subsequent instruction. The processor determines the most recent subsequent instruction based on the combined evictor tag in response to a flush event, and unsets all the evictor tag valid bits set by the most the most recent subsequent instruction along with all previous subsequent instructions.

Imprecise register dependency tracking

Embodiments relate to selection and execution of conditional branch instructions. A computer system is configured with a processing core, including an instruction fetch unit and an instruction sequence unit, operatively coupled to memory. The instruction fetch unit fetches instructions from instruction cache and searches the fetched instruction for any conditional branch instructions. For each conditional branch instruction, an associated confidence level assigned to the instruction is obtained. The instruction sequence unit dispatches conditional branch instructions with their confidence level to a branch issue queue (BRQ). In addition, the instruction sequence unit prioritizes the conditional branch instructions in the BRQ based on the assigned confidence level and age, and selects one of the conditional branch instructions. A branch execution unit is provided as part of the instruction fetch unit to execute the selected conditional branch instruction, followed by dynamically updated any related non-executed instructions in the BRQ.

Prioritization protocols of conditional branch instructions

Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.

On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor

Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.

Growing community of inventors

Austin, TX, United States of America

Tu-An T Nguyen