Fujitsu Corporation

Tszshing Cheung

Tadashi Ikeuchi

Takatoshi Yagisawa

Yasuhide Kuroda

An adaptive equalizer includes an equalization circuit and an operation number change unit. The equalization circuit includes a plurality of cascade-coupled delay taps. The equalization circuit equalizes an input signal by adding calculation results of the plurality of delay taps. The operation number change unit changes a number of operations of the plurality of delay taps according to an equalization error of the equalization circuit.

Adaptive equalizer and adaptive equalizing method

When a direct-current voltage is applied from a power supply, a signal line generates a standing wave having the &#xbe; wavelength where a starting end of the signal line connected to the power supply is used as a node and a terminating end is used as an antinode. Strips are connected to a ground layer through switches, respectively. The switches switch connection and non-connection of the strips and the ground layer, under the control from a switch controller. By switching the connection and non-connection of the switches, the distance between the signal line and the ground layer is pseudo adjusted and the effective permittivity in a transmission line unit changes. Therefore, the frequency of the standing wave can be adjusted.

Oscillator and phase synchronizing circuit

An analog-to-digital converter is disclosed. An input signal processor sets a voltage of an input signal as an initial value of a signal voltage Vin, subtracts &#xbd;of an input range from the nth (n is a positive integer) signal voltage based on a comparison result output from a comparator, and outputs the (n+1)th signal voltage. A reference voltage source outputs a reference voltage to be compared with the signal voltage output from the input signal processor, the reference voltage being obtained by repeatedly reducing by one half the input range. A comparator compares the signal voltage from the input signal processor with the reference voltage from the reference voltage source.

Analog-to-digital converter and analog to-digital conversion method

The phase interpolator includes two adjustable delaysand, phase comparatorwhich detects a phase difference between a signal delayed by the adjustable delayand a signal delayed by the adjustable delay, an integratorwhich integrates the outputs of the phase comparatorand multipliers-and-which set a control voltage for the adjustable delaysand. The feedback loop comprising phase comparatorand integratorcontrols a delay amount of the adjustable delaythereby securing a phase relation between {ACK, ACKand ICK to achieve a stable ICK phase.

Phase interpolator with adaptive delay adjustment

The phase interpolator includes two adjustable delaysand, phase comparatorwhich detects a phase difference between a signal delayed by the adjustable delayand a signal delayed by the adjustable delay, an integratorwhich integrates the outputs of the phase comparatorand multipliers-and-which set a control voltage for the adjustable delaysand. The feedback loop comprising phase comparatorand integratorcontrols a delay amount of the adjustable delaythereby securing a phase relation between {ACK, ACK} and ICK to achieve a stable ICK phase.

According to an aspect of an embodiment, a substrate for connecting circuit boards comprises: a substrate member having a first surface and a second surface facing each other and a first end and a second end facing each other; a first signal line formed on the first surface of the first end; a second signal line formed on the second surface of the second end; a third signal line connecting the first signal line with the second signal line; a first ground plane arranged on the first surface and surrounding the first signal line; and a portion of the second signal line formed over the first ground, the portion comprising narrower than an other portion of the second signal line.

Relay substrate and substrate assembly

A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit.

Phase detection apparatus and phase synchronization apparatus

A latch includes a precharging unit, a memory logic unit, an input amplifying unit, and a clock synchronization switch. The memory logic unit and the input amplifying unit are arranged in a same transistor level. Thus, the latch has three transistor levels. Further, a current supplyis connected to the memory logic unit to control a current flowing through the memory logic unit.

Latch circuit and deserializer circuit

The frequency divider includes the buffer, the function selectorand the inverter. The output of the function selectoris input to the buffer. The output of the bufferis fed back to the function selectorby two paths. One path includes the inverterand the other does not. The function selectorselects one of the paths in synchronous with input clock CK. At one timing the output of the bufferis flipped by the inverter. At the next timing the output of the bufferis held the same by the function selectorselecting the path not including the inverter

High speed dynamic frequency divider

A coil package which makes it easy to handle a high-frequency cone/pyramid-shaped coil and enhance frequency characteristics without degrading the characteristics of the coil. The cone/pyramid-shaped coil has a conical or pyramidal shape formed by wiring a conductor wire around an outer peripheral surface of a core such that the winding diameter of the coil progressively decreases from one end to the other end of the coil. The coil and a dielectric substrate are integrated with each other by forming a hole for inserting a tip portion of the coil in the dielectric substrate, making the bottom of the hole and a back surface of the dielectric substrate electrically continuous by a via, placing the coil in the hole by directing a small-diameter side of the cone/pyramid-shaped coil to the hole, electrically connecting the bottom of the hole and a tip-side lead wire extending from the coil to each other, and connecting an electrode on a large-diameter side of the coil to an electrode on the dielectric substrate.

Coil package and bias tee package

An electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate. A second signal line connected to an outside connection electrode and a second ground conductor are formed on a second surface of the dielectric substrate. The first ground conductor and the second ground conductor are connected by a plurality of ground conductor via-holes. A substrate-buried signal line connected to the first signal line and the second signal line is provided inside of the dielectric substrate so as to be put between the first ground conductor and the second ground conductor above and below and between the ground conductor via-holes on the right and left.

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Kawasaki, Japan

Tszshing Cheung