Intel Corporation

Tsvika Kurts

Itamar S Kazachinsky

Marcelo Yuffe

Beeman C Strong

Ofer Levy

Zeev Sperber

Efraim Rotem

Jason W Brandt

Ittai Anati

Alexander Gendler

Michael Mishaeli

Julius Yuli Mandelblat

Gabi Malka

Boris Dolgunov

William Penner

Shay Gueron

Alon Naveh

Nitin V Sarangdhar

Kevin Safford

Larisa Novakovsky

Michael W Chynoweth

Rajshree Chabukswar

Doron Orenstien

Gerald A Budelman

Moty Mehalel

David I Poisner

Krishnakanth Venkata Sistla

John H Crawford

Kai Cheng

Doron Orenstein

Ernest Knoll

Alex Waizman

Ofer J Nathan

Zelig Wayner

Ariel Sabba

Kenneth B Oliver

Elias Khoury

William A Hobbs

Stephen J Peters

Ziv Shmuely

Richard B O'Connor

Anthony Wojciechowski

Marcus R Winston

Daniel Skaba

Avner Lottem

Vladislav Mladentsev

Tommy Bojan

Vikas R Vasisht

Maor Kima

Eran Shlomo

Eilon Hazan

Jorge Pedro Rodriguez

Yoni Aizik

John William Horigan

Peter Lachner

Hisham Shafi

Todd M Witter

Stephen J Robinson

Roman Surgutchik

Reuven Rozic

Hermann Gartler

Oded Lempel

Peggy J Irelan

Jeffrey D Gilbert

Geeyarpuram N Santhanakrishnan

Ariel Szapiro

Guillermo Savransky

Avner Kornfeld

Vladislav Kopzon

Ki W Yoon

Michael J St Clair

Haim Lustig

Shani Rehana

Sean T Baartmans

Arie Bernstein

Loren James McConnell

Yaniv Hayat

Rony Ghattas

Michael Israeli

Itai Samoelov

Jason Ratner

Sharon Elmosnino

Brad M Dendinger

Vamsi Krishna Jakkampudi

Anwar Azaarura Zaa'Rura

Afik Sela

Genadi Kazakevich

John M Zavertnik

Alexandra Shainshein

Gilad Shayevitz

Yanir Oz

Avner c/o Intel Corporation Kornfeld

A system can include a host machine connected to a device under test (DUT) by a serial link. The host machine can include a serial interface, such as a Thunderbolt interface, and a memory. The DUT can include a trace data source, a high-speed trace interface (HTI) to receive trace data from the trace data source, a serial interface (such as a Thunderbolt interface), and a PIPE interface connecting the HTI with the serial interface. The HTI is to send the trace data to the serial interface through the PIPE interface. The serial interface is to packetize the trace data into a conforming packet format, and send the trace data as a packet across the serial link to the host machine. The host machine can receive the trace data at the host-side serial interface, store the trace data in memory, and process the trace data for debugging the DUT.

Closed chassis debugging through tunneling

Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

Systems and methods for intellectual property-secured, remote debugging

Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer.

Method and apparatus for protecting trace data of a remote debug session

Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Supporting hang detection and data recovery in microprocessor systems

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

Processor core power event tracing

An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

Core-only system management interrupt

In one embodiment, a distributed arbitration system for an interconnect includes: a first transmitter to output first data and a transmit identifier associated with the first data; and a first arbiter coupled to the first transmitter to receive the first data and to arbitrate between the first data and second data from a second arbiter coupled to the first arbiter, based at least in part on a change in a state of the transmit identifier. Other embodiments are described and claimed.

System, apparatus and method for performing distributed arbitration

A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.

High-speed debug port using standard platform connectivity

In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

Using thresholds to gate timing packet generation in a tracing system

A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Real time instruction trace processors, methods, and systems

Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Changing the clock frequency of a computing device

A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.

Processor that records tracing data in non contiguous system memory slices

Growing community of inventors

Haifa, Israel

Tsvika Kurts