Toyoda Koki Kabushiki Kaisha

Toyoda Machine Works, Ltd.

Tsuyoshi Yokota

Toshihiko Yomogida

Isao Suzuki

Sadamu Kato

Haruhisa Tsuji

Itaru Sakurai

A sequence instruction display system for use with a programmable sequence controller for displaying a desired sequence instruction and the on-off state of the input or output element corresponding thereto. A buffer memory is provided for storing input and output instructions along with the corresponding on-off states transmitted from a program memory of the sequence controller on an on-line basis with the scan of the program memory in the sequence controller. A numeric key is provided to designate an output instruction. A comparator, on detecting the coincidence of the designated output instruction with an output instruction transmitted from the sequence controller, outputs a signal so as to prevent the buffer memory from further storing the input and output instructions. A data display device displays at a time one of the input and output instructions along with the on-off state stored in the buffer memory.

Sequence instruction display system

A sequence instruction display system used with a programmable sequence controller for displaying a desired sequence instruction and the on-off state of the input or output element corresponding thereto. A data processor stores the address data of an input element in an input address register when the on-off state thereof and an input instruction corresponding thereto are displayed. The data processor, when a signal is applied thereto, searches a program storage area for an output instruction having the address data which is stored in the input address register and further searches for an input instruction which concerns the energization of the output element corresponding to the output instruction to thereby enable the operator to find a desired sequence instruction by a simple manipulation.

A programmable sequence controller with a counting function comprises an addressable latch circuit including at least one flip flop. A counter is connected to the flip flop such that the content of the counter is changed by one each time the flip flop is set. A setting device is provided for manually setting a count-up value of the counter. A comparator generates a count-up value signal when the counting-up of the counter to the count-up value is detected. A data selector is connected to receive the count-up value signal for supplying a logical value indicative of the status of the comparator. A logic operation circuit is responsive to a test command of a first instruction for testing a logical value of one of a plurality of external input devices and the data selector specified by address data in the first instruction and also responsive to an output command in a second instruction for generating an output command signal based upon the result of the test. The flip flop is set in response to the output command signal generated from the logic operation circuit when the flip flop is designated by the address data.

Programmable sequence controller with counting function

A programmable sequence controller wherein a logic operation processor controls a program counter so as to successively read out from a sequence memory sequence instructions, which are applied to an input and output selector for selectively designating a plurality of input and output elements as well as to the logic operation rocessor. The logic operation processor is programmed to test the operational states of one or more input elements when receiving test commands and to output an energization or deenergization signal based upon the test result when receiving an output command. An output drive device is provided, which energizes or deenergizes selected one of the output elements in response to the energization or deenergization signal. Each of the sequence instructions includes therein any of an arithmetic operation command and the test and output commands, and when the arithmetic operation command is read out, an interrupt is applied to an arithmetic operation processor, which is thus enabled to execute the arithmetic operation command.

Programmable sequence controller with an arithmetic operation function

A programmable sequence controller wherein in accordance with a sequence program read out from a memory, a logic operation circuit tests a logical value supplied from an input converter connected to an external input element and generates an output command signal based upon the result of the test. The output command signal is stored in an output memory which has two storage addresses for each external output element, each storage address corresponding to a particular memory storage element addressed by the sequence program. A gate circuit is connected to these two memory storage elements and inhibits the application of an output command signal from one of the memory storage elements to an output converter when the gate circuit receives a logical value from the input converter. When receiving an output command signal from the other of the two memory storage elements the gate circuit then applies this signal to the output converter. Thus, an output element connected to the output converter is energized immediately in response to the operation of an input element.

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Okazaki, Japan

Tsuyoshi Yokota