Mitsubishi Denki Kabushiki Kaisha

Tsuyoshi Yamada

Tetsuo Tada

In a test assist circuit for a semiconductor device, an address input selector (14a) is so switched that an external address signal is supplied to an address decoder (4) to address a memory circuit (3), while an input data selector (14b) is so switched that external input data is stored in an input data register (5), to be stored in addressed memory elements. Information of the most significant bit of the input data register is stored in an input data information storage area (16), and information of the least significant bit of the address decoder is stored in an address decoder information storage area (15). Data read from the memory circuit is stored in an output data register (6), to be outputted to a data output terminal (9) with the information stored in the address decoder information storage area and that stored in the input data information storage area respectively. Thus, the input data information and the address decoder information added to the outputted data are so observed that a determination can be easily made as to whether the memory circuit is in failure or the test assist circuit is in failure, even if the data read from the memory circuit is in failure.

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Hyogo, Japan

Tsuyoshi Yamada