Micron Technology Incorporated

Elpida Memory, Inc.

Tsuyoshi Tomoyama

Toshio Sugano

Atsushi Hiraishi

Satoshi Isa

Masahiro Yamaguchi

Fumiyuki Osanai

Naoyoshi Kobayashi

Masanori Shibamoto

Hiromitsu Oshima

Keisuke Otsuka

Tomohiro Iwaki

An apparatus includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and a plurality of word-lines extending in parallel across the memory cell region and the peripheral region; a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region.

Semiconductor device and method of forming the same

Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.

Methods for forming openings in conductive layers and using the same

Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having bitline contacts, and methods of forming integrated assemblies

Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.

Patterning methods

Integrated assemblies having bitline contacts

A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor devicehas a semiconductor substrateon which a memory cell area MC defined by a peripheral isolation region. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation regionto separate the memory cell isolation regionsfrom the peripheral isolation region

Semiconductor device having shallow trench isolation structure

A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.

Growing community of inventors

Hiroshima, Japan

Tsuyoshi Tomoyama