Fujitsu Corporation

Tsuyoshi Tomita

Masaru Sawada

Koji Horibe

Hideaki Tanishima

Tsunehiko Moriuchi

Manabu Nakano

Kenichi Yamakura

Yoshitaka Nakata

Fumiaki Uematsu

A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Signal processor having feedback loop control for decision feedback equalizer

A signal processing circuit used in a hard disk controller is able to quickly match its clock signal with preamble data read from a hard disk. The signal processing circuit includes a decision feedback equalizer (DFE) that equalizes a digital read signal in accordance with a clock signal. A timing recovery PLL generates the clock signal having a phase which is coincident with a phase of the digital read signal. The DFE includes a first filter for filtering the digital signal, a decision circuit for adding a feedback signal to the filtered digital signal and generating a decision signal based on the value of the addition. A shift register is connected to the decision circuit and samples the decision signal in accordance with the clock signal, and stores the sampled signal as sampling data. A feedback filter filters the sampled data and feeds it back to the decision circuit. A loop control circuit monitors the filtered digital signal and the feedback signal and controls the feedback loop based on the values of these signals.

Signal processing circuit for preventing pseudo lock of timing recovery PLL

A signal processing circuit for processing a read signal corresponding to data read from a recording medium, such as a magnetic disc. The signal processing circuit detects a preamble data signal of the read signal. A decision feedback equalizer (DFE) generates a computation read signal by performing a predetermined computation on the read signal in accordance with a clock signal. The DFE generates first code data using the computation read signal. A code data generating circuit connected to the DFE compares the computation read signal with a first reference signal and generates second code data, which corresponds to the preamble data signal. A phase error detection circuit detects a phase error between the clock signal and the read signal using one of the first and second code data. A timing recovery PLL is connected to the phase error detection circuit and uses the detected phase error to generate the clock signal such that the phase of the clock signal matches the phase of the preamble data signal.

Signal processing circuit with timing recovery PLL

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Kasugai, Japan

Tsuyoshi Tomita