Mitsubishi Denki Kabushiki Kaisha

Tsuyoshi Takayama

Takaaki Shirasawa

Natsuki Tsuji

Yasuo Koutake

In a circuit having MOS transistors connected in series, a surge voltage that occurs during off periods is reduced, while suppressing an increase in switching loss at turning off of the MOS transistors. When a first power MOSFET ( ) is turned off and then a second power MOSFET ( ) is turned on after that according to predetermined timing, the first power MOSFET ( ) is temporarily placed in an on state for a predetermined time period synchronized with that predetermined timing. On the other hand, when the second power MOSFET ( ) is turned off and then the first power MOSFET ( ) is turned on after that according to predetermined timing, the second power MOSFET ( ) is temporarily placed in an on state for a predetermined time period synchronized with that predetermined timing.

Gate drive device for reducing a surge voltage and switching loss

An IGBT ( ) and a diode ( ) are joined onto an element arrangement portion ( ) of a first terminal member ( ) and an element arrangement portion ( ) of a second terminal member ( ) is joined onto the IGBT ( ) and the diode ( ). Further, an IGBT ( ) and a diode ( ) are joined onto the element arrangement portion ( ) of the second terminal member ( ) and an element arrangement portion ( ) of a third terminal member ( ) is joined onto the IGBT ( ) and the diode ( ). A transfer mold package ( ) is so formed as to house the elements ( ). External connection portions ( ) of the terminal members ( ) are drawn out of the package ( ). The element arrangement portion(s) ( ) of the first and/or third terminal member ( ) are/is exposed out of the package ( ).

Growing community of inventors

Fukuoka, Japan

Tsuyoshi Takayama