Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Elpida Memory, Inc.

Tsuyoshi Tabata

Hideyuki Matsuoka

Masahiro Moniwa

Kazuo Nakazato

Hiroshi Kujirai

Shuji Ikeda

Takashi Hashimoto

Toshiaki Yamanaka

Kousuke Okuyama

Yasuko Yoshida

Keiichi Yoshizumi

Kazushi Fukuda

Soichiro Hashiba

Kazuo Yoshizaki

Fumiyuki Kanai

Kazushi Tomita

Satoru Haga

Koichi Imato

Chiemi Hashimoto

Kohji Yamasaki

Teruo Kisu, Legal Representative

Haruko Kisu, Legal Representative

Motoko Kawashima

Junichi Takano

Mitsugu Oshima

Teruo Kisu

Haruko Kisu

A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film () constituting the channel forming region from an n type poly-crystalline silicon film () constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (); and reducing an effective impurity concentration in the poly-crystalline silicon film ().

Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device

A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.

Method of manufacturing semiconductor device having a plurality of trench-type data storage capacitors

Method of manufacturing semiconductor device and semiconductor device

A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Semiconductor integrated circuit device having capacitance element and

Semiconductor integrated circuit device and process of manufacturing the

Growing community of inventors

Futaba, Japan

Tsuyoshi Tabata