Fujitsu Semiconductor Limited

Digital Vision Laboratories Corporation

Fujitsu Microelectronics Limited

Tsuyoshi Sakata

Toshio Hino

Tomoyuki Yamada

Yusuke Tanefusa

Seiichiro Yamaguchi

Katsuya Ogata

Hiroki Miyaoka

Takanori Hiramoto

Norihiro Harada

Yutaka Mizuno

A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.

Layout method and method of manufacturing semiconductor device

In a circuit design support apparatus, a selection unit selects a delay circuit model from among two or more delay circuit models with wire load based on different values of physical parameters relating to wiring, on the basis of a difference value in a physical parameter between a first path and a second path, the first path being from a branch point of a clock signal line for supplying a clock signal to a register model of a semiconductor integrated circuit model to be designed up to a clock signal input terminal of the register model, the second path being from the branch point up to a data signal input terminal of the register model. An arrangement unit arranges the selected delay circuit model on a data signal line connected to the data signal input terminal.

Apparatus and method for supporting circuit design, and semiconductor integrated circuit

A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a design target circuit and a second analysis result relating to a path of the circuit information, the temperature of the area being equal to or higher than a certain temperature; determining an arbitrary cell on a non-critical path from among cells arranged in the area as a target cell for decreasing the area temperature; and outputting a result of the determination.

Support program, design support device, and design support method

A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coefficients; and outputting a correction result.

Verification computer product, method, and apparatus

A simulation method to be implemented in a computer causes the computer to execute a procedure carrying out a weighting with respect to layout parameters of a circuit, which is an analyzing target, based on priority information of cells forming the circuit, and converting the weighted layout parameters into physical characteristics and storing the physical characteristics in a memory part, a procedure converting the physical characteristic read from the memory part into circuit parameters and storing the circuit parameters into the memory part, and analyzing the circuit based on a net list including the circuit parameters read from the memory part.

Simulation method and computer-readable storage medium

By multiplying a square root of a sum of squares of a standard deviation of cells constituting a target circuit by a weight, or by calculating a square root of a sum of squares of a weighted standard deviation of the cells, the standard deviation of delay of the target circuit can be obtained. Using the obtained standard deviation of delay of the target circuit and the delay of the target circuit, timing verification is performed.

Timing analyzer apparatus and timing analysis program recording medium

An information retrieval apparatus having a meta-data specifying section for specifying at least one attribute of information described in various forms of description, and a pattern learning section for creating rules for extracting information including the specified attribute based on the specified attribute.

Apparatus and method for retrieval of information from various

An information retrieving apparatus comprises a retrieve instruction executing means for executing a retrieve instruction based on a retrieval formula described based on an arbitrary schema, a schema conversion means for converting the retrieval formula into another retrieval formula according to another schema based on pregiven rules, and a schema management means for managing the rules for converting the retrieval formula into the other retrieval formula, wherein the retrieve instruction executing means retrieves desired information based on the other retrieval formula. In this case, preferred embodiments are as follows.

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Yokohama, Japan

Tsuyoshi Sakata