Renesas Electronics Corporation

Renesas Electronics America Inc.

Powerchip Technology Corporation

Tsuyoshi Ota

Tetsuo Sato

Tsutomu Kawano

Ryoji Kato

Koji Kashimoto

Takao Hidaka

Hideo Ishii

Fumio Tonomura

Youhei Kengoyama

Kohei Kawano

To suppress the occurrence of system shutdown after long term storage of batteries. A semiconductor device comprises a control unit that controls charging and discharging of a battery cell, and a ROM that stores a power supply capability value which specifies a power supply capacity of the battery cell that can be stably supplied to an application system in which the battery pack is provided. After the battery pack returns from the sleep mode and before the transmission request of the power supply capability value is received from the system, the control [unit performs a power supply capability value updating process of updating the power supply capability value in the ROM to a value smaller than the power supply capability value before the sleep mode.

Semiconductor device and battery pack

A semiconductor device capable of turning a discharge control transistor off faster while maintaining safety is provided. A control unit, in discharge stopping processing, turns a switching element on and executes a first discharge-stopping mode in which the gate voltage of the discharge control transistor is withdrawn via a load and, at a predetermined discharge-stopping mode switching timing, switches to a second discharge-stopping mode in which the gate voltage of the discharge control transistor is withdrawn directly to a low-voltage power source.

Semiconductor device including a boost circuit for controlling switches in a battery pack

A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.

Battery management control method

A cell protection system includes a charge control MOSFET, a charge current detection MOSFET, a discharge control MOSFET, a discharge current detection MOSFET, a charge current detection resistance, a discharge current detection resistance and a control circuit. The charge current detection MOSFET has a drain and a gate common with the charge control MOSFET. The discharge control MOSFET has a drain common with the charge control MOSFET. The discharge current MOSFET has a drain and a gate common with discharge control MOSFET. The charge current detection resistances and the discharge current detection resistance are provided in correspondence to the charge current detection MOSFET and the discharge current detection MOSFET, respectively. The control circuit generates a gate control signal for the charge control MOSFET and the charge current detection MOSFET by using the charge current detection resistance and generates a gate control signal for the charge control MOSFET and the discharge current detection MOSFET by using the discharge current detection resistance.

Cell protection system

A cell protection system includes a charge control MOSFET, a charge current detection MOSFET, a discharge control MOSFET, a discharge current detection MOSFET, a charge current detection resistance, a discharge current detection resistance and a control circuit. The charge current detection MOSFET has a drain and a gate common with the charge control MOSFET. The discharge control MOSFET has a drain common with the charge control MOSFET. The discharge current detection MOSFET has a drain and a gate common with the discharge control MOSFET. The resistancesare provided in correspondence to the charge and discharge current detection MOSFETs. The control circuit generates a gate control signal for the charge control and current detection MOSFETs by using one of the resistances and generates a gate control signal for the discharge control and current detection MOSFETsby using another one of the resistances.

A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Semiconductor device and method of manufacturing the same

In one embodiment of the cold end switch battery management control method, a battery generates an output voltage at a positive terminal thereof. A first control voltage is also generated by an integrated circuit. A gate of a field effect transistor (FET) receives the first control voltage, wherein the FET comprises a drain and a source with the source coupled to a negative terminal of the battery. The FET transmits current towards the battery in response to the gate receiving the first control voltage, wherein the first control voltage is greater than the output voltage, and wherein the first control voltage is less than a breakdown voltage of the integrated circuit.

Cold end switch battery management control method

A non-volatile semiconductor memory device capable of preventing reading failure during the occurrence of the FG-FG coupling effect is disclosed. The non-volatile semiconductor memory device includes a memory cell array, each cell of which stores at least two bits, such as LSB and MSB, using different threshold voltages. In addition, the device includes a control circuit for controlling the data-reading operation of the memory cell array. When the reading operation of the memory cells of a first word line is performed, the memory cells of a second word line adjacent to the first word line are examined to determine whether the writing operation of the MSB is performed. If the writing operation of the MSB is performed, a pre-charge voltage of the bit lines connecting to the memory cells of the first word line is reduced to a predetermined voltage for canceling out the raising of the threshold voltage caused by the coupling effect between gate electrodes.

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Tokyo, Japan

Tsuyoshi Ota