Fujitsu Corporation

Fujitsu Vlsi Limited

Tsuyoshi Ohira

Yoshihiro Takemae

Masao Nakano

Tomio Nakano

Hirohiko Mochizuki

Yukinori Kodama

Hidenori Nomura

Shigeki Nozaki

Seiji Enomoto

Norihisa Tsuge

Takaaki Furuyama

Katsuhiko Kabashima

Hatsuo Miyahara

Meiko Kobayashi

Masaru Satoh

Masakazu Kanai

A dynamic random access memory includes a dummy word line which has an electrical characteristic identical to that of an actual word line. The dummy word line is charged up and is then discharged as in case of the actual word line. A latched row address in a row address latch circuit is reset when the potential of the dummy word line becomes equal to a predetermined low potential due to the discharge operation for the dummy word line.

Dynamic random access memory having dummy word line for facilitating

A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

Semiconductor memory device with internal control signal based upon

A semiconductor memory device having a memory cell array constituted by a plurality of memory cell blocks includes a clock generator unit constituted by a plurality of clock generator sections, each of the clock generator sections corresponding to each of the memory cell blocks, and a block selector unit for selecting one of the clock generator sections in correspondence with the row address of a designated address. Accordingly, only a clock generator section corresponding to the selected memory cell block is operated by the designated address.

Semiconductor memory device capable of selective operation of memory

A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.

Semiconductor memory device having data bus reset circuits

A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.

Semiconductor memory device having data bus reset circuit

A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.

Memory device employing address multiplexing

A transfer gate circuit including a first MIS transistor which transmits an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal supplied to a gate of the first MIS transistor; an inverter circuit connected between power supply lines which inverts the potential of the transmitted input signal; and an output level guarantee circuit comprising second and third MIS transistors which have conductivity type opposite to that of the first MIS transistor and are connected in series between one of the power supply lines and the output side, an output signal of the inverter circuit being supplied to a gate of the second MIS transistor, an inverted signal of the control signal supplied to the gate of the first MIS transistor being supplied to a gate of the third MIS transistor.

Transfer gate circuit protected from latch up

A semiconductor memory device comprises a memory cell array comprising memory cells; a plurality of pairs of bit lines which are coupled to the memory cells and a data bus, each bit line being divided into at least two pairs of bit line parts; at least one sense amplifier provided between the pairs of bit line parts in each of the pairs of bit lines, for sensing a difference in potential between bit line parts in each pair, the sense amplifier being formed with complementary metal oxide semiconductor transistors; and at least a pair of transfer gates provided between a non-data bus side and a data bus side of the sense amplifier, the pair of transfer gates being held in an off-state when the sense amplifier is activated.

Semiconductor memory device having a CMOS sense amplifier

A dynamic semiconductor memory device includes data output lines (D, D), a data output buffer (12), a column enable buffer (9), and an output enable buffer (11) for generating an output enable signal (OE) to enable the transmission of data from the data output lines to the data buffer. The output enable buffer is driven by the clock signals of the column enable buffer. An output disabling circuit (13) is provided to stop the generation of an output enable signal by the output enable buffer when the output enable buffer is not being driven by the column enable buffer. As a result, the data output buffer assumes a high-impedance state when a power supply is turned on.

Semiconductor memory device

A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.

Semiconductor integrated circuit device

In a semiconductor memory device including an output buffer circuit receiving data signals read out from a memory cell array, an output stage MOS transistor being turned ON and OFF according to the output signals of the output buffer circuit, and an output buffer enable (OBE) signal generator circuit for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit, a V.sub.BS voltage generator circuit is provided for generating a voltage V.sub.BS higher than the voltage source V.sub.CC preceding the rising up of the OBE signal, which voltage V.sub.BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly up to a level higher than the voltage source V.sub.CC.

A dynamic semiconductor memory device provides a selected real cell, which is connected to a first of a pair of bit lines connected to a sense amplifier, and a dummy cell which is connected to a second of the pair of bit lines so as to perform a read-out operation. The dynamic semiconductor memory cell further provides an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by the read-out operation. The dynamic semiconductor cell can also provide a write-in circuit for charging the selected real cell through the bit line. A test power source pad is provided in the active restore circuit or the write in circuit so that when the reference level of the real cell is tested an optional power source can be applied from the test power source pad instead of from a normal power source.

Dynamic semiconductor memory device

A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ''.about.DC.sub.2,127 '') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).

Dynamic random access memory device

A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.

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Kawasaki, Japan

Tsuyoshi Ohira