Kabushiki Kaisha Toshiba

Tsuyoshi Nishikawa

Mototsugu Hamada

Toshiyuki Furusawa

Masafumi Takahashi

Yoshiro Tsuboi

A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.

Semiconductor integrated circuit device

A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area, formed on the semiconductor chip, which operates at a second voltage and a second frequency lower than the first voltage and the first frequency, respectively, and also operates after a shift to the first voltage and the first frequency; and a third area, formed on the semiconductor chip, which operates at the first voltage and a frequency which operates the second area and transmits and receives signals sent between the first area and the second area; the third area possessing a delay analysis endpoint that can analyze each of a first delay occurring between the first area and the third area and a second delay occurring between the second area and the third area.

Semiconductor integrated circuit and method of testing delay thereof

A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.

A motion pictures sending apparatus has a camera interface for receiving an image signal from a camera, a frame conversion unit for carrying out coordinates conversion on the received image signal and generating image data, a memory for storing the image data, an image processing unit for processing the image data from the memory and providing processed data, an output interface for transferring the processed data to a communication interface unit, and a memory control unit for stopping the updating of image data to the memory in response to an input signal. When required, the apparatus keeps the same image in the memory and continuously sends the image so that the quality and clarity of the sent image may gradually improve.

Motion pictures sending apparatus and motion pictures communication apparatus

In a memory consolidated image processing LSI for reading data, a DRAM for storing image data for a plurality of page ranges which are formed by segmenting an image plane corresponding to a display screen in order to page-access a memory region of the DRAM, and image data for a plurality of word ranges which are formed by segmenting each of the page ranges in order to word-access the memory region, is consolidated with an image processing circuit. The size of each of the page ranges is set so that the multiplied value of the power consumption per pre-charge in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value, and the size of each of the word ranges is set so that the multiplied value of the power consumption per word access in the power consumption model of the memory by an average number of word accesses is the substantially minimum value. Thus, it is possible to reduce the power consumption when a page access and a word access are carried out, so that the memory consolidated image processing LSI can be mounted on a portable image processing system.

Memory consolidated image processing LSI, image processing system with same, and image accessing method using same

A motion vector estimation circuit includes an assigning element having a grouping part for dividing candidates in a search range into a plurality of groups, and a part for determining the order for accumulation being carried out preferentially from a group having a high possibility of including a true motion vector; an accumulating element for parallel inputting original image data and reference image data to accumulate an absolute value of a difference between both data according to the order determined by the assigning element; a circuit for comparing the output of the accumulating element with minimum-value information for management; a stopping element having a separate stop circuit for stopping operations of each of the accumulating circuits after detecting the minimum-value information; and a control element for controlling the accumulating element and the stopping element.

Motion vector estimation circuit and method

A motion vector estimating system comprises a current image storing unit 1, a reference image storing unit 2, a motion vector estimating circuit 3 for estimating a motion of a current image in relation to a reference image, and a global motion vector estimating circuit 10. The global motion vector estimating circuit 10 comprises at least a feature setting part 11 for setting and recording a feature being a partial region distinguishable from other regions of a principle object in a picture, a feature-coordinates extracting part 12 for searching the current image for the feature to extract the coordinates of the feature, and a feature-coordinates storing part 13 for storing the coordinates of the feature. When the feature-coordinates extracting part 12 extracts the coordinates of the feature from the current image, the motion vector estimating system derives a difference between the feature coordinates stored in the storing part 13 and the extracted feature coordinates on the basis of a feature presence information outputted from the feature-coordinates extracting part 12, in order to estimate a global motion vector. When the feature-coordinates extracting part 12 has not could extract the feature, the motion vector estimating system carries out the usual motion vector estimation. Thus, in addition to the usual motion vector estimation, the presence and coordinates of a feature are extracted from the whole screen of a picture to detect a motion vector to retrieve a correct motion vector at the initial stage of the retrieval, so that it is possible to save the electric power and decrease the estimation time.

System for estimating motion vector with instant estimation of motion

A motion vector estimating system prepares a predetermined range of a frame/field of image data as a macro block, selects a plurality of proposed motion vectors in the reference region, calculates a signal-strength difference between pixels corresponding to each of the proposed motion vectors of current and reference images. The system comprises: an accumulating element for deriving an accumulation result in parallel on the basis of the signal-strength difference by means of accumulating circuits connected in parallel as a pipeline; an accumulation stopping element having separate stop circuits for separately stopping the accumulation of the accumulating element every n accumulating circuits; and a control element for controlling the supply of the current image data and the reference image data for proposed motion vectors for each of the accumulating circuits, and for outputting a separate stop signal to the accumulation stopping element for stopping the accumulation for the proposed motion vector of the accumulating circuits immediately after the accumulated value of the absolute values of the differences between the signal values of picture elements of the current image and the reference image exceeds a predetermined value. Thus, it is possible to suitably omit unnecessary accumulation in a pipeline processing for estimating a motion vector, so that it is possible to increase the processing speed and to decrease the electric power consumption.

Growing community of inventors

Kawasaki, Japan

Tsuyoshi Nishikawa