Sharp Kabushiki Kaisha Corporation

Japan Radio Co., Ltd.

Sharp Corporation

Tsuyoshi Muramatsu

Shinichi Yoshida

Souichi Miyata

Motoki Takase

Hiroshi Tanaka

Manabu Yumoto

Atsushi Aoki

Takashi Morisue

Manabu Onozaki

Ryuji Miyama

Masaharu Tomita

Tatsuyuki Kuwabara

Kiyotaka Nagamura

Takao Nakamura

Ryuji Kadosumi

Toshiya Okamoto

Shingo Kamitani

Hidekazu Yamanaka

Kouichi Hatakeyama

Takeshi Kameda

Ricardo T Shichiku

Kazuya Arakawa

Shin'ichi Yoshida

Masayuki Ehiro

Takahiko Nakano

Daisuke Azuma

Tomoya Ishikura

Hiroshi Kanekura

Takayuki Amagai

Atsushi Tokura

Takashi Horiyama

Yasufumi Itoh

Shingo Nomura

Takuji Urata

Katsumi Arata

Takuji Uneyama

Yasuhiro Matsuura

Kouichi Hatakekyama

Toshiaki Terasaka

Kohichi Hatakeyama

In a transmissive liquid crystal display device including a liquid crystal panel and a backlight, the liquid crystal panel has pixels each divided into four subpixels, namely red (R), green (G), blue (B), and white (W) subpixels. Further, the backlight is a white backlight whose light emission luminance is controllable. Furthermore, a color-saturation conversion section performs a color-saturation reduction process on a first input RGB input signal serving as an original input signal, and then a gamma-correction section performs a gamma-correction process on the first RGB input signal. An output signal generation section calculates transmittances and a backlight value in accordance with gamma-corrected RGB input signal obtained after the gamma-correction process has been performed by the gamma-correction section.

Transmissive liquid crystal display device having color saturation conversion section

In a transmissive liquid crystal display device including a liquid crystal panel and a backlight, the liquid crystal panel contains pixels each divided into four subpixels, a red (R), a green (G), a blue (B), and a white (W) subpixel. The backlight is a white backlight emitting light with controllable emission luminance. A luminance lowering section performs luminance lowering processing on input RGB signals (original input signals) for transformation into luminance-lowered RGB signals. An output signal generating section obtains transmittances and a backlight value from the luminance-lowered RGB signals.

Transmissive liquid crystal display device having control section for controlling emission luminance of backlight

In a transmissive-type liquid crystal display device including a liquid crystal panel and a backlight, the liquid crystal panel has pixels each divided into four subpixels red (R), green (G), blue (B), and white (W). The backlight is a white backlight by which luminance of emitted light is controllable. A color-saturation reducing section carries out a process of reducing color saturation on a first RGB input signal, which is an original input signal, so that the first RGB input signal becomes a second RGB input signal. Thereafter, an output signal generating section obtains a transmissivity and a backlight value on the basis of the second RGB input signal.

Transmissive-type liquid crystal display device

The transmission liquid crystal display device includes a liquid crystal panel and a backlight, wherein the liquid crystal panel has pixels each of which is divided into four sub pixels as red (R), green (G), blue (B), and white (W) sub pixels. Further, an emission luminance of the backlight can be controlled.

Transmission liquid crystal display device

Each of image data sorted so as to correspond to divided areas respectively is stored in an in-area image memory. A maximum luminance extracting section extracts the maximum luminance value therefrom and records it onto the maximum luminance storage section. In accordance with the maximum luminance value that is thus stored in the maximum luminance storage section and that each of the areas has, a BL candidate value calculating section and a BL luminance difference adjusting section determine an emitted-light luminance in a target area such that a difference between the backlight luminance in the target area and the backlight luminance in its adjacent area is not more than a tolerance value.

Transmissive display device

A branching control unit includes a logic gate and a NAND circuit that can receive transfer permission for each branching designation. The branching control unit further includes a transfer request unit receiving respective outputs of the logic gate and NAND circuit. The transfer request unit sends a data transfer request to a branching designation when the logic gate or NAND circuit is rendered active. Since transfer permission can be received for each branching designation to send a transfer request, a data waiting state depending upon the data holding state of another branching destination will no longer occur. Thus, a data driven type information processing apparatus and method of transferring a data packet at higher speed in a data transmission path can be provided.

Data driven type information processing apparatus and method of increasing transfer speed of data packet

A self-synchronous FIFO memory device () has a structure in which n self-synchronous data transmission lines (-) are arrayed in parallel. An input control section () selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a first transfer request signal, a first acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a preceding-stage section. Further, an output control section () selects one of the n self-synchronous data transmission lines, and mediates the reception and delivery of a second transfer request signal, a second acknowledge (transfer instruction) signal and data between the selected self-synchronous data transmission line and a self-synchronous data transmission line of a succeeding-stage section.

Self-synchronous FIFO memory device

A data-driven type information processor includes a ifinction processor manipulating contents in a data packet, a program storage unit storing a data flow program used by the function processor, and a branch unit controlling data flow whether to allow flow of a data packet within the processor or to provide the data packet to the outside thereof When a program is debugged, the portion of the program where a data packet is to be dumped (and checked) is directly designated by writing an instruction in a program that is stored in advance in the program storage unit. When the instruction code is encountered, the packet is dumped to the outside so that debugging of the program can be carried out by confirming the contents in the data packet that is output.

Data transfer for debugging in data driven type processor processing data packet with data flow program including transfer control bit setting instruction

In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a function of controlling transfer operation is used, by which the number of packet copies output from a data holding register is managed by a counter, and the number of copies represented by the copy request packet and the counter count value are compared by a comparator, to determine completion of the packet copying operation.

Data driven type information processing apparatus

An address calculation unit calculates a plurality of addresses corresponding to a plurality of data included in a data packet. A first bank memory access unit accesses a first bank memory according to a first address calculated by the address calculation unit. Simultaneously, a second bank memory access unit accesses a second bank memory according to a second address calculated by the address calculation unit. A packet reconstruction unit reconstructs the data packet according to the results of access by the first and second bank memory access units. Accordingly the processing rate of the data packet including a plurality of data is increased.

Data-driven information processing device and method to access multiple bank memories according to multiple addresses

A C element controls a pipeline register and successively transfers data packets. When a dead-lock state occurs, a data packet in the pipeline register is erased by a master reset signal, a host transfer flag operating circuit overwrites a data packet in the pipeline register so that it has a host transfer flag at the 'H' level, and thereafter, when the host transfer flag is detected in the subsequent stage, the data packet is transferred to the host.

Data driven type information processing apparatus having deadlock breaking function

When the cache memory unit reads the last word of a page of the cache memory, the external memory interface reads ahead data of a prescribed number of pages ahead of the relevant page. Thus, data corresponding to the access request to the external main memory is always held in the cache memory. This prevents degradation of parallel processing capability of the data driven type information processing apparatus.

External memory control device regularly reading ahead data from external memory for storage in cache memory, and data driven type information processing apparatus including the same

When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the self-synchronous transfer control circuit, when a data transfer enabling signal is applied from a C element in a subsequent stage, a node number manipulation circuit manipulates a node number to make copies such that packets can be distinguished from each other, and then data is transferred from a pipeline register to a pipeline register in a subsequent stage.

Self-synchronous transfer control circuit and data driven information processing device using the same

A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, including a page address, a set value for setting an effective bit and data, and an address generating unit for generating an address for accessing the data memory by retrieving effective data from the data included in the data packet based on the set value and attaching the page address included in the data packet to the retrieved effective data.

Data-driven type information processing apparatus and information processing method allowing for effective use of memory

A data driven type processing device has an error diffusion computing unit built therein. An error holding register is provided within the error diffusion computing unit, and is used to successively store and update a value of error information of a pixel that is to be diffused to a neighboring pixel being processed continuously. An error data memory is provided outside the computing unit, and is used to store and update a value of the error information that is to be diffused to another neighboring pixel being processed discontinuously. The error information and the values to be diffused are stored in a packet, and the packet is circulated for operation.

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Nara, Japan

Tsuyoshi Muramatsu