Fujitsu Corporation

Tsuyoshi Mori

Seishi Okada

Akihiro Kurihara

A cache controller expresses a status of a data block by one of six statuses obtained by newly adding Writable Modified to Invalid, Shared, Exclusive, Modified, and Shared Modified. In response to a fetching request from a self system CPU for a data block having the status of Invalid I, when the data block having the status of Modified M is obtained from a cache apparatus of another system, the cache controller changes the status of the obtained data block from Invalid to Writable Modified. The cache controller also switches the status of the data block on the obtaining destination side from Modified to Invalid. As a result, the making of a status change notification to the other system in response to a subsequent storing request from the self system CPU, is unnecessary.

Cache apparatus and control method having writable modified state

An instruction fetch control system prefetches a branch instruction in a pipeline system and fetches a branch target instruction of the branch instruction. The control system comprises a first branch judgement circuit for conducting a branch condition judgement in a stage prior to the branch judgement stage in which a second and original branch judgement of the branch instruction is conducted, and a circuit for starting a prefetch of instructions following said branch target instruction without waiting for the branch judgement stage where the first branch judgement circuit judges that the branch is successful.

Instruction pipeline with a branch prefetch when the branch is certain

A microcode reading control system in an information processing system wherein a machine instruction is divided into microcode instructions as a plurality of steps, each step is further divided into a plurality of stages, and the stages of the microcode instructions are processed in parallel with advanced retrieval control, a first aspect of which provides duplexed control storages storing the microcode instructions read in at a first step of the machine instruction, one of the control storages being read only at the first step of a branch target machine instruction of a branch machine instruction, and a second aspect of which provides a first control storage storing microcode instructions to control the first steps of the machine instructions and a second control storage storing microcode instruction to control the second steps and thereafter of the machine instructions, the first control storage reading the stored microcode instruction at the second stage of the first step of the machine instruction, and the second control storage reading at the first stage of the second step and thereafter of the machine instructions. Thus, in a processing of the branch machine instruction, the control can be accelerated.

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Kawasaki, Japan

Tsuyoshi Mori