Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Kabush″ei Kaishr Toshiba

Tsuyoshi Midorikawa

Shigeyuki Hayakawa

Yutaka Tanaka

Toshiaki Dozaka

Toshiaki Douzaka

Tadashi Onizawa

A semiconductor storage device according to an embodiment comprises: a first memory circuit; a second memory circuit having a storage capacity smaller than that of the first memory circuit; a readout line commonly connected to the first memory circuit and the second memory circuit; a sense amplifier configured to compare a voltage of a first bit signal or a second bit signal with a reference voltage, where the first bit signal being inputted from the first memory circuit through the readout line and the second bit signal being inputted from the second memory circuit through the readout line; and a readout conditioning circuit configured to change at least one of an operation timing of the sense amplifier and the reference voltage corresponding to the first bit signal and the second bit signal.

Semiconductor storage device including sense amplifier that senses data from multiple memory circuits

According to one embodiment, there is provided a semiconductor memory device including a bit cell, a pair of bit lines and an assist circuit. The pair of bit lines are electrically connected to the bit cell. The assist circuit is configured to be connected to the bit lines and including one or more capacitive elements. A ratio between a parasitic capacitance value of each of the bit lines and a capacitance value of the assist circuit is adjustable.

Semiconductor memory device with write assist control

According to one embodiment, there is provided a semiconductor storage device including bit cells, a pair of bit lines, a word line, a write amplifier, a word line driver, and an assist timing control circuit. The pair of bit lines are electrically connected to the bit cells. The word line is electrically connected to the bit cells. The write amplifier is electrically connected to the pair of bit lines. The word line driver is electrically connected to the word line. The assist timing control circuit has an output side electrically connected to the write amplifier and the word line driver.

Semiconductor storage device with assist timing control circuit

A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.

Semiconductor memory device with delay circuit and sense amplifier circuit

A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.

Fuse-data reading circuit

A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.

Growing community of inventors

Yokohama, Japan

Tsuyoshi Midorikawa