Panasonic Corporation

Socionext Inc.

Tsuyoshi Koike

Yoshinobu Yamagami

Hidenari Kanehara

Yasuhiro Agata

Akira Masuo

Norihiko Sumitani

Kazuki Tsujimura

Shigeo Houmura

Noriaki Narumi

Youji Nakai

Yuichirou Ikeda

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

FINFET based driver circuit

Finfet based driver circuit

A memory bank of a semiconductor memory device includes: a plurality of memory cells; first and second local bit lines; a differential amplifier configured to amplify a potential difference between the first and second local bit lines; a connector to which a global data line is connected; a first output circuit configured to selectively output, according to a potential level of the first local bit line, a first potential to the connector; and a second output circuit configured to selectively prevent, according to a potential level of the second local bit line, a potential of the connector from being affected by an output of the first output circuit and being equal to the first potential.

Static semiconductor memory device using a single global data line

A comparison function-equipped memory element includes: a memory circuit that stores comparison object data; a comparison circuit that compares the comparison object data held in the memory circuit with comparison data and outputs the comparison result; and a write circuit that writes the comparison object data into the memory circuit under control of a write control signal during write operation, and overwrites the comparison data into the memory circuit when a mask control signal indicates mask operation during comparison operation.

CAM cell for overwriting comparison data during mask operation

A cross-coupled circuit provided between first and second bit lines that form a bit line pair includes first to fourth fin transistors of p-channel type. The first transistor has its source connected to a first power supply and its gate connected to the second bit line. The second transistor has its source connected to the first power supply and its gate connected to the first bit line. The third transistor has its source connected to the first transistor's drain and its drain connected to the first bit line. The fourth transistor has its source connected to the second transistor's drain and its drain connected to the second bit line.

Semiconductor storage device and sense amplifier circuit

There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.

Semiconductor integrated circuit

A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.

Input circuit

The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of the local bit line pairs and connect the selected local bit line pair to the global bit line pair; and a sense amplifier connected to the global bit line pair. The sense amplifier is controlled by a sense amplifier activation signal to which the outputs of the plurality of voltage change detection circuits are connected, whereby the voltage of a selected read data line pair is amplified using discharge of a non-selected read data line pair, to achieve high-speed read.

Data transmission circuit and semiconductor memory device including the same

In a semiconductor memory device, an update data control circuit is provided, which selectively couples a physical address input data line or an effective address input data line to a common input data line coupled to a physical address cell that stores a physical address page number. A control terminal of an update circuit of the physical address cell is coupled to a page size cell that stores page size information via an update control circuit, to control a write port of the physical address cell with the page size cell.

Semiconductor memory device

A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.

A power supply control circuit which can cut off a power supply independently is provided for each column in a memory cell array. The power supply control circuit is controlled by a circuit which is provided for each column and determines whether or not it is necessary to hold information, whereby a power supply for a memory cell which does not need to hold information is cut off.

In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is fixed or permanently stored in the memory cell while ensuring a resistance to damage to the gate of the transistor and without impairing the regularity of the layout.

A memory cell () includes a read circuit () whose output wiring is a read bit line (RBIT) and which has a switching transistor (), a reset transistor (), and an output wiring driving transistor (). The switching transistor () connects a data holding node (MD) of a storage circuit () and a control line (DR) in accordance with a control signal on a read word line (/RWL). The reset transistor () resets the control line (DR) in accordance with a reset control signal (RST). The output wiring driving transistor () has a gate connected to the control line (DR), a drain connected to the read bit line (RBIT), and a source connected to a ground power supply.

Semiconductor storage device

A dummy memory cell for detection of write completion timing is provided as a replica of a memory cell. When assisting a write operation by power supply control and substrate potential control of the memory cell, the timing of ending the write assist operation is determined by a voltage control circuit based on information about the dummy memory cell. For example, the voltage control circuit performs, in a data write operation in the memory cell, the write assist operation of decreasing the voltage of a source power supply allocated to P-channel MOS load transistors using a pull-down transistor. Thereafter, at the time when completion of the data write operation in the dummy memory cell is detected, the voltage control circuit ends the write assist operation and restores the voltage of the source power supply to the original level using a pull-up transistor.

Static semiconductor memory with a dummy call and a write assist operation

A voltage of a bit line connected to a memory cell is stepped up up to a power supply voltage by a precharge circuit. Before data is read from the memory cell, the voltage of the bit line is stepped down to a voltage level lower than the power supply voltage by a step-down circuit. A precharge switching element controls a connection between a high-potential-side power supply and the precharge circuit and a connection between a low-potential-side power supply and the precharge circuit. A power supply connecting circuit is provided between the precharge switching element and the high-potential-side power supply. A ground connecting circuit is provided between a connecting point at which the precharge switching element is connected to the power supply connecting circuit and the low-potential-side power supply.

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Shiga, Japan

Tsuyoshi Koike