Renesas Technology Corp.

Renesas Electronics Corporation

Synaptics Corporation

Tsuyoshi Koga

Motoi Ashida

Daisuke Okada

Hiroji Ozaki

Tsutomu Okazaki

Masahiro Shimizu

Shinya Suzuki

Yoshiyuki Ishigaki

Kazuyuki Misumi

Tatsuhiko Akiyama

Yuichi Nakagomi

Yasuhiro Fujii

Tomohiro Murakami

Naoyuki Narita

Kazuhiko Sato

Akio Nishida

Jun Shibata

Takashi Terada

Yukio Maki

Naoki Hasegawa

Hiroshi Tobimatsu

Kazuhito Matsukawa

Tomohiro Hosokawa

Yoshiko Higashide

Yasuichi Masuda

Makoto Dei

Kiyotaka Miwa

A flexible connector comprises a first plurality of pads disposed within an integrated circuit (IC) area, a second plurality of pads disposed in the IC area, and a plurality of through holes disposed in the IC area. The flexible connector further comprises first wiring coupled to the plurality of through holes and the first plurality of pads, and a rigidity element at least partially disposed between the plurality of through holes and the second plurality of pads.

Flexible connector for a display device

A semiconductor device comprises a semiconductor substrate, a connection pad, and a bump. The connection pad is connected to the bump and disposed between the semiconductor substrate and the bump. The connection pad has one or more slits.

Connection pad configuration of semiconductor device

A method for manufacturing a magnetic memory chip device comprises the steps of: writing information in each of a plurality of magnetic memory chips formed on a silicon wafer; adhering a high magnetic permeability plate on a back face of the silicon wafer after writing information, the high magnetic permeability plate having a higher magnetic permeability than silicon and having a thickness of 50 um or more; dicing the silicon wafer into respective magnetic memory chips after adhering the high magnetic permeability plate.

Method for manufacturing magnetic memory chip device

A method for manufacturing a magnetic memory chip device comprises the steps of: writing information in each of a plurality of magnetic memory chips formed on a silicon wafer; adhering a high magnetic permeability plate on a back face of the silicon wafer after writing information, the high magnetic permeability plate having a higher magnetic permeability than silicon and having a thickness of 50 &#x3bc;m or more; dicing the silicon wafer into respective magnetic memory chips after adhering the high magnetic permeability plate.

A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Semiconductor device having electrode and manufacturing method thereof

Semiconductor device having a split gate structure with a recessed top face electrode

In a semiconductor chip A wherein an element layerhaving transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 &#x3bc;m or less, and thereafter, a gettering layeris formed on the back face of the semiconductor chip A. The gettering layeris formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Semiconductor chip having gettering layer, and method for manufacturing the same

A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Semiconductor memory device

A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T . At least a portion of the latch circuit is formed above the bit line.

Semiconductor memory device having a latch circuit and storage capacitor

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Tokyo, Japan

Tsuyoshi Koga