Fujitsu Corporation

Shinko Electric Industries Co., Ltd.

Tsuyoshi Kanki

Yoshihiro Nakata

Yasushi Kobayashi

Akio Rokugawa

Sadahiro Kishii

Masato Tanaka

Shinya Sasaki

Shoichi Suda

Noriyoshi Shimizu

Nobuyuki Ohtsuka

Hisaya Sakai

Takahiro Kimura

Junya Ikeda

Tetsuya Shirasu

A semiconductor device includes a printed circuit board that includes a first electrode, a resin substrate that includes a first face directed toward the printed circuit board, a second electrode formed in a second portion surrounding a first portion of the first face, a second face opposite the first face, and a third electrode formed in a third portion of the second face, the third portion overlapping the first portion in a plan view, a semiconductor chip that includes a coupling terminal joined to the third electrode, a conductive member that is formed between the printed circuit board and the resin substrate and contains a conductive particle and resin, and a solder bump that is formed between the printed circuit board and the resin substrate and is joined to the first electrode and the second electrode.

Semiconductor device, electronic device, method of manufacturing semiconductor device, and method of manufacturing electronic device

A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring layers includes a fine wiring, a barrier film, which is not in contact with the fine wiring, is formed at a more outer side from the base board than the wiring layer including the fine wiring, and different types of resin insulating films are used for a wiring layer at an inner side of the barrier film close to the base board and a wiring layer at an outer side of the barrier film, respectively.

Wiring board including multiple wiring layers

After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu&#x2014;N&#x2014;R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu&#x2014;N&#x2014;R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.

Interconnection structure and method of forming the same

A semiconductor device includes a copper interconnect provided in a trench in an insulation film, a metal film provided on the insulation film along a boundary between the insulation film and the copper interconnect, a barrier metal provided between an inner wall of the trench and the copper interconnect and extending over the metal layer, a first metal cap to cover the copper interconnect and the barrier metal located over the metal film, and a second metal cap to continuously cover the first metal cap, the barrier metal and the metal film.

Semiconductor device and manufacturing method having copper interconnects with metal film, barrier metal, and metal caps

A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.

Wiring structure and manufacturing method thereof, and electronic apparatus and manufacturing method thereof

A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Semiconductor device and its manufacture method

A manufacturing method of a semiconductor device includes: forming an insulating layer above a substrate; forming a recessed section in the insulating layer; forming, on the insulating layer, a mask pattern having a first opening which exposes the recessed section, and a second opening which is arranged outside the first opening and does not expose the recessed section; forming a first conductive member and a second conductive member by respectively depositing a conductive material in the first opening and the second opening; and polishing and removing the first conductive member and the second conductive member on the upper side of the insulating layer so as to leave the first conductive member in the recessed section.

Manufacturing method of semiconductor device and semiconductor device

(a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300&#xb0; C. or higher at a temperature rising rate of 10&#xb0; C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.

Manufacture method for semiconductor device using damascene method

A method for manufacturing a semiconductor device, including depositing an interconnect material including Cu or Cu alloy over an insulating film, and polishing the interconnect material by CMP with a polishing liquid, wherein the oxidation-reduction potential (ORP) of the polishing liquid is controlled so as to be in the range of 400 mV to 700 mV vs. Ag/AgCl.

Growing community of inventors

Atsugi, Japan

Tsuyoshi Kanki