Rohm Co., Ltd.

Tsuyoshi Hosono

Toshiyuki Kanaya

The semiconductor device includes a semiconductor layer having a main surface, a first semiconductor region of a first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a second semiconductor region of a second conductivity type formed in a surface layer portion of the first semiconductor region and forming a zener diode with the first semiconductor region, a third semiconductor region of the first conductivity type formed in the surface layer portion of the first semiconductor region separated from the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in a region between the second semiconductor region and the third semiconductor region in the surface layer portion of the first semiconductor region and having a second conductivity type impurity concentration less than a second conductivity type impurity concentration of the second semiconductor region, and an insulating layer formed on the main surface of the semiconductor layer and covering the second semiconductor region, the third semiconductor region and the fourth semiconductor region.

Zener diode with semiconductor region annularly surrounding anode

A semiconductor device includes a semiconductor layer having a main surface, a gate insulating film including a thin film portion forming a tunnel window, a thick film portion formed around the thin film portion and having a thickness larger than a thickness of the thin film portion, and an inclined portion connecting the thin film portion and the thick film portion and inclined upward from the thin film portion toward the thick film portion, and covering the main surface of the semiconductor layer, a memory gate structure formed on the thin film portion of the gate insulating film, and a select gate structure formed on the thick film portion of the gate insulating film.

Semiconductor device with suppression of electric field concentration

A semiconductor device includes a gate insulating film formed on the semiconductor substrate; a floating gate formed on the gate insulating film; a control gate formed on the floating gate and has a side coplanar with a side of the floating gate; a tunnel diffusion layer facing a portion of the floating gate; and a tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window being formed to be thinner than a remaining peripheral portion of the gate insulating film.

Growing community of inventors

Kyoto, Japan

Tsuyoshi Hosono