Hitachi, Ltd.

Renesas Technology Corp.

Other

Pioneer Electronic Corporation

Asahi Kasei Microdevices Corporation

Honda Motor Co., Ltd.

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Tokyo Electronics Co., Ltd.

Tsuyoshi Fujiwara

Toshinori Imai

Kenichi Takeda

Junji Noguchi

Hidenori Sato

Hiromi Shimamoto

Yoshinori Hoshino

Hiroshi Ashihara

Takeshi Saikawa

Kazutoshi Oomori

Katsuyuki Asaka

Daichi Matsumoto

Yasuhiro Nariyoshi

Tsuyoshi Ishikawa

Toshiyuki Mine

Masaki Saito

Nobuaki Miyakawa

Koji Hiramatsu

Katsuhiko Ichinose

Kiyomi Katsuyama

Naohumi Ohashi

Makoto Miura

Toshiro Koyanagi

Yoshifumi Saeki

Saburo Takaoka

Minoru Kosaka

Toshio Saito

Tsutomu Suzuki

Hiroki Uemura

Atsushi Hiroshige

Masahiro Ushiyama

Tsutomu Fukui

Yoshiyuki Okabe

Ryouichi Furukawa

Masato Kunitomo

Youichiro Tsuda

Kiyohiko Sato

Toshiaki Iwasaki

Sumitaka Matsumura

Tetsuo Saito

Ryohei Maeno

Seiji Hashimoto

Shozo Nakamuta

Takashi Morii

Toshihiko Hosaka

Akira Otaguro

Yukino Ishii

Satoshi Moriya

Yoshinobu Sawamoto

Shunichi Katsumata

Goichi Yokoyama

Hiroyuki Miyata

Osamu Tazawa

Tetuo Kanazashi

Morihisa Oka

Tsutomu Miyazaki

Akira Ootaguro

Yoshihiro Kawasaki

Yuji Imamura

Toyohiko Kuno

Tomohiro Shiraishi

Masaaki Yoshida

Tetsuo Kanazashi

Yoshinori Kawasaki

Mitsuhiro Toya

Katsuaki Matsumoto

Kiyohiko Satoh

Shunji Mori

Kuniaki Shiratori

A step of forming a stacked film serving as a lower electrode, a step of forming an insulating film serving as a capacitive film on the stacked film, and a step of patterning the insulating film and the stacked film are performed. In the step of forming the stacked film, a film containing titanium, a film containing titanium and nitrogen, a main conductive film containing aluminum, a film containing titanium, and a film containing titanium and nitrogen are sequentially formed from below. The ratio of the surface roughness of the upper surface of the stacked film to the thickness of the insulating film is 14% or less.

Manufacturing method of semiconductor device and semiconductor device

The orientation polarization (positive and negative) of the Si&#x2014;N bonds and the Si&#x2014;O bonds is canceled, thereby enabling to minimize the polarization in a capacitive insulating film. As a result, a silicon oxynitride film with a small voltage secondary coefficient is formed, and is applied as a capacitive insulating film for use in a MIM capacitor. Specifically, the refractive index 'n' of the silicon oxynitride film satisfies 1.47&#x2266;n&#x2266;1.53, for light with a wavelength of 633 nm.

Transistor with MIM (Metal-Insulator-Metal) capacitor

The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.

Semiconductor device and method for manufacturing the same

A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS&#x2022;FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.

A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Semiconductor device and manufacturing method of the same

Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

Semiconductor device, RF-IC and manufacturing method of the same

A resistor Rformed by forming a first resistor layerof 20 nm thickness including a tantalum nitride film at a concentration of nitrogen of less than 30 at % and a second resistor layer of 5 nm thickness including a tantalum nitride film at a concentration of nitrogen of 30 at % or more successively by a reactive DC sputtering method using tantalum as a sputtering target material and using a gas mixture of argon and nitrogen as a sputtering gas, and then fabricating the first and the second resistor layers, in which the resistance change ratio of the resistor can be suppressed to less than 1% even when a thermal load is applied in the interconnection step, by the provision of the upper region at a concentration of nitrogen of 30 at % or more.

The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal interconnect. The MIM capacitor is realized by forming an interlayer dielectric film comprising silicon oxide so as to cover the first metal interconnect, then forming a first opening in the interlayer dielectric film to a region corresponding to a via hole layer in the interlayer dielectric film just above the first metal interconnect so as not to expose the upper surface of the first metal interconnect, then forming a second opening to the inside of the first opening so as to expose the surface of the first metal interconnect and then forming a capacitance film and a third metal interconnect.

Manufacturing method of semiconductor device

In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

Method of manufacturing semiconductor device having MIM capacitor

An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

Semiconductor device comprising metal insulator metal (MIM) capacitor

In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride filmfor self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400&#xb0; C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride filmconstituting a passivation film is formed at a substrate temperature of about 350&#xb0; C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride filmis smaller than that contained in the silicon nitride film, making it possible to suppress hydrogen release from the silicon nitride film

Semiconductor integrated circuit device and process for manufacturing the same

It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750&#xb0; C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60&#xb0; C./second or less.

Method for manufacturing semiconductor integrated circuit device

Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main component, a second insulating film formed over the upper surface and side surfaces of each of the interconnects and over the first insulating film and having a function of suppressing or preventing copper diffusion, and a third insulating film formed over the second insulating film and having a dielectric constant lower than that of the second insulating film; and a method of manufacturing the semiconductor device. This invention makes it possible to improve dielectric breakdown strength between copper interconnects and reduce capacitance between the copper interconnects.

Semiconductor device including an interconnect having copper as a main component

Disclosed is a method of manufacturing a semiconductor device which has reliable buried interconnects (wirings) and a reliable MIM capacitor. An interconnect and a capacitor bottom electrode are formed inside a hole made in six insulation films. Then a barrier insulation film is formed on the uppermost film (of the above six insulation films) including the interconnect and the top face of the bottom electrode. After two insulation films are formed above the barrier insulation film, a hole is made in the two insulation films and a capacitor top electrode is buried in that hole. The barrier insulation film also functions as a capacity insulation film for the capacitor. Then, after three other insulation films are formed on the upper film (of the above two insulation films) including the top face of the top electrode, a hole is made in the barrier insulation film, the two insulation films, and the three other insulation films, and another interconnect is buried in that hole.

Semiconductor device manufacturing method

Growing community of inventors

Hamura, Japan

Tsuyoshi Fujiwara