Renesas Electronics Corporation

Tsuyoshi Eda

Shinji Watanabe

Akira Matsumoto

Hirokazu Honda

Satoshi Matsui

Toru Sekiguchi

Yoshitaka Kyougoku

In order to reduce the number of electrodes included in test patterns, the semiconductor integrated circuit includes, a plurality of first and second chains, a first common electrode connected to one end of each first chain, a second common electrode connected to one end of each second chain, and a plurality of selection electrodes. Each selection electrode is connected to the other end of any one of the plurality of first chains and to the other end of any one of the plurality of second chains. When a test target chain is selected from the plurality of first chains, a first reference voltage is applied to the first common electrode, a second reference voltage is applied to a target selection electrode that is connected to the test target chain, and a current flowing in the target selection electrode is measured to obtain a resistance value of the test target chain.

Semiconductor integrated circuit, and method for testing semiconductor integrated circuit

A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.

Semiconductor device

The present invention provides a semiconductor device for which thermal stress at mounting is reduced and a reduction in reliability with regard to moisture absorption is prevented. The semiconductor device includes a uppermost metal layer, a solder bump, metalsandwhich connect an uppermost metal layerand the solder bump, and, a polyimide multilayerhaving formed therein an openingin which the metalsandare provided. The polyimide multilayerincludes a first polyimide layerA and a second polyimide layerB formed on the first polyimide layerA. The second polyimide layerB is softer than the first polyimide layerA. A thermal stress at mounting is reduced by the second polyimide layerB. Since the first polyimide layerA has a higher strength than the second polyimide layerB, even if cracking occurs in the second polyimide layerB, the cracks are prevented from developing in the first polyimide layerA.

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Kanagawa, Japan

Tsuyoshi Eda