Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Socionext Inc.

Tsuyoshi Ebuchi

Takefumi Yoshikawa

Toru Iwata

Yoshihide Komatsu

Yukio Arima

Michiyo Yamamoto

Kyoko Hirata

Tatsuo Okamoto

Kenji Murata

Junji Nakatsuka

Takashi Hirata

Shinya Miyazaki

Seiji Watanabe

Yuji Yamada

Tsuyoshi Hiraki

Satoshi Hori

Disclosed herein is a signal potential converter which may perform high-speed operation and which may still maintain intended signal amplitude and operate normally even while operating at a low rate or receiving a burst signal. In this signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential at the terminal node, i.e., a signal IN, within the range of a first potential to a second potential. If a potential at the terminal node is higher than a third potential, a voltage holder circuit operates to raise the potential at the terminal node. If the potential at the terminal node is lower than the third potential, the voltage holder circuit operates to lower the potential at the terminal node.

Signal potential converter

An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.

Interchannel skew adjustment circuit

A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.

Hybrid data transmission circuit

A spread spectrum controller () controls a PLL () so that the PLL outputs a spread-spectrum processed clock signal. A loop bandwidth controller () controls at least one of a phase detector (), a loop filter (), a voltage-controlled oscillator (), and a frequency divider () in the PLL () during operation of the spread spectrum controller () to change a loop bandwidth of the PLL ().

Spread spectrum clock generation device

An AC-coupled interface circuit on a semiconductor integrated circuit apparatus performing a bidirectional data transfer via a differential transmission line includes a differential driver, a differential receiver and a potential setting section. The differential driver includes a pair of output terminals connected to a pair of signal lines. The differential receiver includes a pair of input terminals connected to the pair of signal lines. In a data transmission operation, the differential driver converts transmit data to a differential signal to output the differential signal. In a data reception operation, the differential receiver receives a differential signal transferred to the pair of signal lines and converts the differential signal to receive data. The potential setting section sets a potential of the pair of signal lines to a predetermined stable potential before the differential signal is transferred to the pair of signal lines.

AC-coupled interface circuit

A calibration circuit () adjusts at least one of one of a charging current of a charge pump circuit () and a capacitance value of a filter capacitor in a loop filter circuit () and a gain of a voltage controlled oscillator (), depending on a frequency of a reference clock signal input to a calibration circuit ().

Spread spectrum control PLL circuit and its start-up method

A PLL comprises a current-controlled oscillator () for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (), and an initialization switch () for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator () and the current source ().

PLL circuit

A multiphase clock generation circuit () for generating a multiphase clock signal, a phase subdivision unit () for shifting a phase of the multiphase clock signal output from the multiphase clock generation circuit (), and a clock selection unit () for selecting one of clock signals output from the phase subdivision unit () are provided. A PLL circuit () for receiving an output from a frequency division circuit () is further provided. The phase shift carried out by the phase subdivision unit () and the selection of the clock signal carried out by the clock selection unit () are controlled by a frequency control unit () to switch SSC ON/OFF and to change the bandwidth of the PLL circuit ().

Clock generation circuit having a spread spectrum clocking function

In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Receiver circuit

The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

Frequency modulation circuit

The driver circuit of the present invention includes: a drive section for generating a differential signal according to an input signal and outputting the signal to an electric cable or an optical transceiver; and a control section receiving a selection signal based on which the drive section selects to drive the electric cable or the optical transceiver, an identification signal, and a data signal, for generating a signal based on the received signals and outputting the generated signal to the drive section. During a period indicated by the identification signal, the control section controls the drive section to put the output of the drive section in a high impedance state when the selection signal indicates selection of the electric cable, or output a predetermined differential signal, not putting the output in a high impedance state, when the selection signal indicates selection of the optical transceiver.

Driver circuit and data communication device

The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.

Growing community of inventors

Osaka, Japan

Tsuyoshi Ebuchi