Other

Texas Instruments Corporation

Tsuyoshi Akiyama

Hiroshi Miyaguchi

Yoichiro Miki

Naoya Tokunaga

Kenta Sokawa

Yuji Yaguchi

Kazuki Ninomiya

Masahiro Tani

Kenya Adachi

Hidetoshi Onuma

The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP core of this SVP (Scan-line Video Processor) is made up of a three layer construction of the data input register (DIR) the SIMD type digital signal processing unit and the data output register (DOR) The SIMD type digital signal processing unit comprises a parallel arranged (connected) number of processing elements (PE to PEN&minus;1) (for example, 864 units) equal to the number of pixels N on one horizontal scan line. The instruction generator (IG) because the SVP core operates as an SIMD parallel processor, internally houses a RAM or ROM program memory that holds the desired program. The program stored in program memory contains not only the instructions (SIMD instruction) for the processing elements (PE to PEN&minus;1) of the processing unit but also such instructions (IG instruction) as jump, subroutine call, hardware interrupt, and the like. In this SVP when an IG instruction is read from the program memory while the repetitive processing of an SIMD instruction is being conducted in the SVP core the pertinent IG instruction is executed in parallel with the repetitive processing of the pertinent SIMD instruction.

Processor

A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Memory interface device and memory address generation device

A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

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Tsuchiura, Japan

Tsuyoshi Akiyama