Mitsubishi Denki Kabushiki Kaisha

Zeon Corporation

Mitsubishi Electric Engineering Company, Limited

Tsutomu Yoshimura

Naoya Watanabe

Yasunobu Nakase

Yoshikazu Morooka

Harufusa Kondoh

Hiromi Notani

Kei Sakamoto

Hiroshi Makino

Shinya Ikeda

Satoshi Kiriki

Norio Higashisaka

Masahiko Ishiwaki

Tomonori Ogawa

Kiyonori Umetsu

Harufusa Kondo

Jingo Nakanishi

Hironobu Ito

Masanobu Shinohara

Kengo Takata

Jun Takaso

Ryuji Mano

Taiki Herai

Shigeki Kohama

Tomohito Yamanoue

Satoshi Nishio

A method for recovering an unreacted &#x3b1;,&#x3b2;-ethylenically unsaturated nitrile monomer contained in a latex of a nitrile rubber obtained by emulsion polymerizing a monomer mixture comprising an &#x3b1;,&#x3b2;-ethylenically unsaturated nitrile monomer and a carboxyl group-containing monomer is provided. The method includes the steps of: adjusting a pH of the latex of the carboxyl group-containing nitrile rubber to 6.5 or more; decompressing the latex of the carboxyl group-containing nitrile rubber having the pH adjusted to 6.5 or more under a heating condition; and recovering a component evaporated by the decompression under the heating condition.

Method for recovering unreacted alpha, beta-ethylenically unsaturated nitrile monomer contained in latex of carboxyl group-containing nitrile rubber

A method for producing a carboxyl group-containing nitrile rubber including the steps of: polymerizing a monomer mixture including an &#x3b1;,&#x3b2;-ethylenically unsaturated nitrile monomer and a carboxyl group-containing monomer in a solvent; terminating a polymerization reaction by adding a nitrous acid salt and a water-insoluble hydroquinone as polymerization terminators to the polymerization system, thereby obtaining a dispersion of the carboxyl group-containing nitrile rubber having a pH of 7 or below; and coagulating the dispersion of the carboxyl group-containing nitrile rubber, thereby obtaining the carboxyl group-containing nitrile rubber in the solid state, wherein the amount of the nitrous acid salt to be used is 0.15 parts by weight or less relative to 100 parts by weight of the monomer mixture used in the polymerization reaction.

Method for producing carboxylated nitrile rubber

A method of producing a carboxyl group-containing nitrile rubber including a coagulation step of coagulating a carboxyl group-containing nitrile rubber component by mixing a monovalent metal salt and a polymer flocculating agent into a carboxyl group-containing nitrile rubber latex having an iodine value of 120 or less, wherein the monovalent metal salt is compounded in an amount of 3 to 25 parts by weight and the polymer flocculating agent is compounded in an amount of 0.01 to 10 parts by weight relative to 100 parts by weight of a rubber solid content in the latex, and a weight ratio of the monovalent metal salt/the polymer flocculating agent is in the range of 10 to 500

Method for producing carboxyl-group-containing nitrile rubber

An acrylic rubber composition which contains, with respect to 100 parts by weight of acrylic rubber, a compound which is expressed by the following general formula (1) in 0.1 to 50 parts by weight and a cross-linking agent in 0.05 to 20 parts by weight is provided. 

Acrylic rubber composition and cross-linked rubber product

An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Automatic frequency correction PLL circuit

An amplifier circuit includes a first differential amplifier circuit, a second differential amplifier circuit which amplifies an output signal from the first differential amplifier circuit, and an active feedback circuit which performs waveform shaping on the output signal from the first differential amplifier circuit by feeding back an output signal from the second differential amplifier circuit. The active feedback circuit includes first and second transistors having collectors or drains respectively connected to respective output nodes of the first differential amplifier circuit, bases or gates respectively connected to two output nodes of the second differential amplifier circuit, and emitters or sources connected in common, and a first current source which has a first end connected to the emitters or sources of the first and second transistors, and a second end connected to a low-voltage power supply, and producing a current that can be externally adjusted.

Amplifier circuit

A differential charge pump circuit has two current paths and generates a differential current in accordance with currents inputted to the two current paths. The two current paths have a pair of current sources respectively and form a differential pair. The differential charge pump circuit has controlling means for detecting an output potential difference between the two current paths and controlling current values of the current sources in accordance with the output potential difference.

Differential charge pump circuit

The present digital synchronous circuit includes a clock generating circuit for outputting a plurality of clock signals CLKto CLKn, a plurality of first latch circuits, each for receiving an input data signal DIN at a data input terminal and for receiving a corresponding clock signal at a clock input terminal, a plurality of second latch circuits, each for latching, in response to the receipt of a control signal LC, an output signal from a corresponding first latch circuit, and a control circuit for receiving input data signal DIN to generate control signal LC. Control circuit outputs control signal LC after a delay of a prescribed period of time after the change in input data signal DIN. As a result, the adverse influence of the meta-stable state that occurs when sampling an asynchronous input data signal DIN is avoided, while at the same time, the chip size and power consumption are limited.

Digital synchronous circuit for stably generating output clock synchronized with input data

An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V) in the capacitor (). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V) in a capacitor (). A differential amplifier circuit () generates appropriate voltages (Vand V) according to a design specification of the transistors (and) by amplifying the voltage values (Vand V) and outputs them. The voltages (Vand V) are impressed on respective back gates of the transistors (and), respectively.

Input buffer circuit having function of canceling offset voltage

A frequency comparator detects the phase of a data signal DATA by using four-phase clocks ICLK, /ICLK, QCLK and /QCLK as a reference and detects a change in the phase. A counting processing unit counts a period in which a control signal UP or DN is activated within a predetermined period, and outputs an overflow detection signal LOL if the frequency is high. A hysteresis generating unit changes a signal LOL to the L level only after signal LOL goes low X times consecutively. On the other hand, after signal LOL is set to the L level once, the hysteresis generating unit changes signal LOL to the H level only after signal LOL goes high X times consecutively. With such a configuration, a phase-locked state detecting circuit with reduced malfunction even when a data signal having larger jitter is input can be provided.

Frequency comparator with malfunction reduced and phase-locked state detecting circuit using the same

A signal according to a phase difference in a first phase-locked loop is transferred to a power supply line as an operation power supply voltage for a first oscillation circuit included in the first phase-locked loop. The potential of the power supply line is supplied to a second oscillation circuit in a second phase-locked loop as an operation power supply voltage. The second phase-locked loop is used to generate a clock signal phase-synchronized to the input clock signal. Consequently, a clock generator is implemented that oscillates at a central frequency to generate a recovered clock signal even when a variation is caused in a manufacturing parameter.

Clock generator for generating internal clock signal synchronized with reference clock signal

A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit ( ) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit ( ) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit ( ) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

Digital data transmission system

A circuit module includes a connector terminal ( A) provided on a front surface of a printed wiring board ( ) and connected to a data pin (DQ ) of a memory IC ( ) through an interconnect line ( ). A conductive connector terminal ( ) corresponds to the connector terminal ( ) and is provided on a back surface of the printed wiring board ( ). A through hole ( ) extends between part of the front surface of the printed wiring board ( ) where the connector terminal ( ) is formed and part of the back surface thereof where the conductive connector terminal ( ) is formed. A conductor fills the through hole ( ), thereby suppressing skews resulting from a difference in interconnect line length on the circuit module and decreasing a stub capacitance to achieve the reduction in power consumption.

Circuit module

A clock circuit is provided including a clock supply circuit that can cease clock supply according to a control signal, a PLL circuit maintaining clock synchronization, and a dummy circuit. Synchronization of the internal clock signal is maintained by the PLL circuit and the dummy circuit even in a standby state. In returning to an active state from a standby state, an unstable clock signal arising from unstable locking of the PLL circuit will not be applied to the internal circuit. Therefore, the information in the latch circuit in the internal circuit can be maintained.

Semiconductor device that can have standby current reduced by ceasing supply of clock signal, and that can maintain status of internal circuit

A differential VCO includes a ring oscillator with a plurality of differential buffers connected in a ring, a bias circuit including a replica circuit of the differential buffers, and a differential gain increasing circuit for increasing differential gain of the differential buffers. Even when the differential gain of the differential buffer lowers as a result of obtaining a clock signal of higher frequency, the ring oscillator oscillates smooth.

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Tokyo, Japan

Tsutomu Yoshimura