Fujitsu Corporation

Tsutomu Taniguchi

Mitsutaka Ikeda

Yoshikazu Homma

First transistor rows are arranged, each including two transistors connected in series for selectively connecting any of memory cell rows to an input/output circuit. A switching transistor operates as a switch and a short transistor(s) each having a source and a drain shorted to each other function(s) as wiring. The first transistor rows are provided with a plurality of transistors in advance. Since there is no need to selectively form only such a transistor that is to be operated as a switch, there is no need to form ion-implanted regions for making a source and a drain per transistor. As a result, the spacing with which the transistors are arranged can be set without considering the layout rule of the diffusion layer regions. Since the transistors can be arranged closely, the layout area can be decreased and the chip size of the semiconductor memory can be reduced.

Semiconductor memory

A semiconductor memory device comprises a detecting unit and a testing unit. The detecting unit detects a plurality of times a state of a predetermined terminal when the power is switched on, and activates the testing unit when all results of the detections show expected values. The device shifts to a connection testing mode by activation of the testing unit, and performs predetermined testing. Therefore, the testing can be performed by causing the device to shift to the testing mode without using terminals dedicated to testing. Besides, a shift to the connection testing mode by activation due to an erroneous operation or power-supply noise is prevented from occurring. In another semiconductor memory device the conversion circuit receives parallel testing patterns via a plurality of input terminals and converts the patterns into serial output patterns. Since the parallel testing patterns are converted into serial output patterns, connection testing can be performed even when the number of output terminals is small. Furthermore, another semiconductor memory device comprises an operation circuit and a conversion circuit. The operation circuit receives parallel testing patterns via a plurality of input terminals, performs a logic operation, and outputs parallel operation result patterns. The conversion circuit receives the parallel operation result patterns and converts the patterns into serial output patterns. The converted output patterns are sequentially output from output terminals. The testing patterns fed to the conversion circuit by the operation circuit can be reduced. Accordingly, the output patterns become shorter, and testing time is reduced.

Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board

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Kawasaki, Japan

Tsutomu Taniguchi