Kabushiki Kaisha Toshiba

Tsutomu Takei

Hiroshi Imai

Yasuo Yamada

Atsushi Masuda

Masafumi Takahashi

Takeshi Kitahara

Masatoshi Sekine

Hiroaki Nishi

Masami Aihara

Kazuyoshi Kohno

Katsuhisa Kondo

An assertion description conversion device comprising: verification target identification unit parsing the syntax of a high-level assertion description described by a high-level assertion description language for verification of an inputted design description of a broader term to identify a verification target; design description searching unit searching a description on the verification target in a design description of a broader term; verification target description conversion unit converting the description of the verification target into a design description of a narrower term according to the design description of the narrower term corresponding to the description searched by the design description searching unit; verification content analysis unit for analyzing verification contents for the verification target described in the high-level assertion description; and verification content description conversion unit for converting the verification contents analyzed by the verification content analysis unit into the description format of a low-level assertion description language for verification of a design description of the narrower term.

Assertion description conversion device, method and computer program product

A simulation system for verifying logic behavior of a semiconductor integrated circuit includes a reprogrammable semiconductor device having an interface circuit and a logic circuit; and an analyzing unit dividing a logic behavior of the semiconductor integrated circuit into a software-based first logic behavior and a hardware-based second logic behavior and generating circuit data of the interface circuit included in the first logic behavior that exhibits an input/output behavior and circuit data of the logic circuit that exhibits the second logic behavior.

Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit

A design support device 1 has a module division and merger section 8 for receiving a result from a HDL analysis section 6 to analyze a HDL description of a RTL and for dividing and merging the modules based on instructions from outside or automatically, a module allocation section 10 for allocating the modules by using the result from the module division and merger section 8 and the analyzed result by the HDL analysis section 6, a budgeting section 11 for budgeting an area, a shape, a timing, and a power consumption to each of the modules allocated by the module allocation means 10, and an estimation section for estimating module information for the result from the module division and merger section 8 and the result from the module allocation section 10.

Design support system in which delay is estimated from HDL description

Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them. The data base comprises a region for storing a statement correspondence table expressing statements as descriptions of the logical functions of the circuit components, a region for storing a circuit component table expressing a circuit component corresponding to the function described in the statement, a region for storing a dependent relationship table expressing the dependent relationship between the statements, and a correspondence relationship table expressing the correspondence relationship between the statement correspondence table and the circuit component table.

Test assistant system for logical design process

A pulse input device has a standard time generator for outputting standard time information by counting a system clock signal; an input circuit for sampling input signal information from a plurality of channels in synchronization with the standard time information at a predetermined period; a memory for storing the input signal information sampled by the input circuit; a command memory for storing a plurality of instruction commands; and a controller for scanning the instruction commands stored in the command memory to successively execute the instruction commands, for repeating the scanning operation of the instruction commands, and for controlling operations of the device. The controller outputs a designation signal having a period of a predetermined time for designating an execution starting time obtained by counting the system clock signals, so that the period of the execution starting time for each of the instruction commands becomes a constant rate in the successive command scanning operation for successively executing each of the instruction commands in synchronization with the designation signal, and the period of the predetermined time is set based on the instruction command having the longest execution time.

Growing community of inventors

Kanagawa-ken, Japan

Tsutomu Takei