Hitachi, Ltd.

Hitachi Microcomputer System, Ltd.

Tsutomu Sumimoto

Masanori Odaka

Hideo Sawamoto

Mitsugu Kusunoki

Shuuichi Miyaoka

Michiaki Nakayama

Kazuhisa Miyamoto

Masao Kato

Kouji Kobayashi

Toshihisa Taniguchi

Takashi Ogata

Masato Ikeda

Takashi Kumagai

A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Semiconductor integrated circuit device

When an IOP is transferring data at the maximal throughput because of the fact that the input-output processor (IOP) has issued a next request under a state when the request buffers are full of requests from the IOP at least a part of the requests from the instruction processor (IP) is inhibited. Inhibition of the requests from the IP is released when the pitch of the requests from the IOP reaches a predetermined period or more. When the IOP is transferring data at the maximal throughput in a system having a cache memory, access to the main memory by the IP is inhibited in case requested data does not exist in the cache memory.

Memory access control unit for allowing maximum throughput of an I/O

A memory access control system for an information processing apparatus having a buffer memory and a main memory wherein when a store or access request is generated, in the case where the data block in the address to be accessed does not exist in the buffer memory, the store requested data from a data register is written into the buffer memory before the first data in the data block read out from the main memory is written into the buffer memory, and the data register is released to receive the next request.

Advanced store-in system for a hierarchy memory device

Growing community of inventors

Hadano, Japan

Tsutomu Sumimoto