Tokyo Shibaura Denki Kabushiki Kaisha

Sensor Technos Co., Ltd.

Tsutomu Sakamoto

Keizo Aoyagi

Michio Arai

Yukio Shiraogawa

Chikara Shimamura

To discriminate counterfeit articles by incorporating invisible ID information recording apparatus in the true articles. An LC resonance tag 1 is buried in the articles 21 and 22 at the time when they are being produced in compliance with the contraction of a license. Upon bringing transmission and reception antenna units 15, 16 of a reflected wave analyzer 11 close to the articles, the resonance frequencies of the LC resonance tags 1 are specified, and voice messages such as brand, name of article, explanation of article, etc. are produced from a speaker of the reflected wave analyzer 11 based on the display data related to the resonance frequencies, verifying that the articles are true ones.

Method of displaying information by using an LC resonance tag

A microinstruction-controlled arithmetic control unit including an inhibiting circuit enables prohibition, when parallel operation is not possible in the same cycle, of the execution of the succeeding microinstruction by the inhibiting circuit without the insertion of dummy microinstructions, and permits parallel operation, when parallel operation is possible in the same cycle, by releasing the function of the inhibiting circuit, thereby improving the operation speed.

Microinstruction controlled arithmetic control unit

A microprogram-controlled type arithmetic control apparatus which performs pipeline processing is provided. In the apparatus, a microinstruction corresponding to a macroinstruction to be processed are read out of a control storage at least one stage prior to an OF (operand fetch) stage. The microinstruction and data (source data) are respectively output onto a microinstruction bus and a data bus at the OF stage. By the beginning of an E (instruction execution) stage, data (source data) on the data bus and the microinstruction on the microinstruction bus are loaded into first and second registers, respectively. Then, at the beginning of the E stage, arithmetic operation by an arithmetic and logic unit can be performed immediately.

Arithmetic control apparatus for a pipeline processing system

A fixed-point data/floating-point data converting apparatus has: a priority encoder with input terminals respectively receiving output signals from logic gates (first logic gates) for use in detecting whether or not all of the digits fixed-point data are '0', to obtain a number of continuous 'zero' digits from the most significant digit of the fixed-point data, in accordance with the contents of the signals received thereby; a shifter for shifting the fixed-point data to the left by the number of digits of continuous 'zero' digits, thereby obtaining a mantissa part; an adder for subtracting the number of continuous 'zero' digits from a reference value, thereby obtaining an exponent part; and a data selector for generating the floating-point data in accordance with the subtraction results from the adder, the shift results from the shifter, all-zero data, and an output signal from the logic gate (first logic gate) for detecting whether or not all digits of the fixed-point data are '0', in response to the output signals from the logic gates (second logic gates). In this converting apparatus, the data selector selects the all-zero data, as floating-point data, when all of the digits of the fixed-point data are '0'. Otherwise, the data selector selects, as floating-point data, data including the subtraction results supplied from the adder and the shift results supplied from the shifter.

Fixed-point data/floating-point data converting apparatus

According to a shift circuit of the present invention, two single-word length data shifters of 2.sup.n bits are arranged in parallel. Further, a selective output section is provided to selectively supply the upper 2.sup.n bits or the lower 2.sup.n bits of the double-word length data of 2.sup.n+1 bits, sign of the data and constant to an individual section in accordance with the number of the shift and the type of shift such as the shift direction, arithmetic shift or logical shift. One shifter produces the upper 2.sup.n bits of the shifted data as a result of the shift operation of the double-word length data of 2.sup.n+1 bits, and the other shifter produces the lower 2.sup.n bits thereof while the two shifters operate independently in accordance with the same contents of a shifting number register.

Shift circuit for double word length data

An input/output start instruction includes, as parameters, a channel number, an input/output device number, a channel control block address and a termination que number. A channel receives the channel control block address and reads out the contents of the channel control block from a main memory and sets it in a service table in the channel whereby an input/output processing is executed.

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Tokyo, Japan

Tsutomu Sakamoto