Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Other

Hitachi Automotive Engineering Co., Ltd.

Tsutomu Okazaki

Daisuke Okada

Yasushi Ishii

Toshikazu Matsui

Kyoya Nitta

Toshihiro Tanaka

Digh Hisamoto

Akira Kato

Kan Yasui

Takeshi Sakai

Yoshihiro Ikeda

Masaru Nakamichi

Satoru Machida

Munekatsu Nakagawa

Yuichi Tsukada

Keisuke Tsukamoto

Hiroji Ozaki

Motoi Ashida

Tsuyoshi Koga

Hiroshi Yanagita

Shoji Shukuri

Hiraku Chakihara

Tetsuo Udagawa

Hitoshi Kume

Masataka Kato

Kazuhiro Komori

Toshiaki Nishimoto

Nobukatsu Arai

Shinichi Okamoto

Hiroaki Saeki

Tatsuya Fukumura

Koji Kishi

Yuki Ejiri

Yasunori Murakami

Seiji Sakagami

Koichiro Yamada

Chiaki Niida

Keiichi Haraguchi

Hideki Honma

Masashi Fukaya

Hideo Tobe

A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Semiconductor device

There is improved performance of a semiconductor device including a fin-type low-withstand-voltage transistor and a fin-type high-withstand-voltage transistor. A low-withstand-voltage transistor is formed on each of a plurality of first fins isolated from each other by a first element isolation film, and a high-withstand-voltage transistor, which has a channel region including tops and side surfaces of a plurality of second fins and a top of a semiconductor substrate between the second fins adjacent to each other, is formed. At this time, a top of a second element isolation film surrounding the second fins including part of the channel region of one high-withstand-voltage transistor is lower than a top of the first element isolation film.

Semiconductor device and method of manufacturing the semiconductor device

Semiconductor device with gate electrodes

A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided. One end of an electricity supply line ESL is arranged over a terminal end TEand the other end thereof is arranged over a terminal end TE, and further, the central portion of the electricity supply line ESL is arranged over a dummy part DMY. That is, the terminal end TE, the terminal end TE, and the dummy part DMY have substantially the same height, and therefore, most of the electricity supply line ESL arranged from over the terminal end TEto over the terminal end TEvia the dummy part DMY is formed so as to have the same height.

Non-volatile memory semiconductor device

For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.

Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device

A non-volatile memory semiconductor device having one end of an electricity supply line ESL arranged over a terminal end TEand the other end thereof arranged over a terminal end TE, the central portion of the electricity supply line ESL being arranged over a dummy part DMY. The terminal end TE, the terminal end TE, and the dummy part DMY have substantially the same height, so that most of the electricity supply line ESL arranged from over the terminal end TEto over the terminal end TEvia the dummy part DMY has the same height.

Semiconductor device with improved common source arrangement for adjacent non-volatile memory cells

A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Semiconductor device having electrode and manufacturing method thereof

Semiconductor device having a split gate structure with a recessed top face electrode

Growing community of inventors

Tokyo, Japan

Tsutomu Okazaki